6dbc01e801
This is a NFC patch. This patch run a bulk update on CodeGen tests that are impacted by the true16 features. This patch applies: 1. duplicate GFX11plus runlines and apply them with "+mattr=+real-true16" and "+mattr=-real-true16" 2. update the test with the update script For some GISEL runlines, the current CodeGen do not fully support the true16 version. Still update the runlines, but comment out the failing one, and added a "FIXME-TRUE16" comment to that test for easier tracking. These test will be fixed in the following patches. This is in a transition state that we support both "+real-true16/-real-true16" in our code base. We plan to move to "+real-true16" as default, and finally remove "-real-true16" mode and test lines.
356 lines
15 KiB
LLVM
356 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-SDAG-TRUE16
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-GISEL-TRUE16
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
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define amdgpu_kernel void @raw_ptr_atomic_buffer_ptr_load_i32(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_ptr_load_i32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB0_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 0 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call i32 @llvm.amdgcn.raw.ptr.atomic.buffer.load.i32(ptr addrspace(8) %ptr, i32 0, i32 0, i32 1)
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%cmp = icmp eq i32 %load, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_off(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_i32_off:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB1_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 0 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB1_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call i32 @llvm.amdgcn.raw.ptr.atomic.buffer.load.i32(ptr addrspace(8) %ptr, i32 0, i32 0, i32 1)
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%cmp = icmp eq i32 %load, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_soff(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_i32_soff:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB2_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 4 offset:4 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB2_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call i32 @llvm.amdgcn.raw.ptr.atomic.buffer.load.i32(ptr addrspace(8) %ptr, i32 4, i32 4, i32 1)
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%cmp = icmp eq i32 %load, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_dlc(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_i32_dlc:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB3_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 0 offset:4 dlc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB3_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call i32 @llvm.amdgcn.raw.ptr.atomic.buffer.load.i32(ptr addrspace(8) %ptr, i32 4, i32 0, i32 4)
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%cmp = icmp eq i32 %load, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_nonptr_atomic_buffer_load_i32(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_nonptr_atomic_buffer_load_i32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 0 offset:4 glc
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: .LBB4_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_and_b32 s1, exec_lo, vcc_lo
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; CHECK-NEXT: s_or_b32 s0, s1, s0
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
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; CHECK-NEXT: s_cbranch_execnz .LBB4_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %ptr, i32 4, i32 0, i32 1)
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%cmp = icmp eq i32 %load, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i64(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_i64:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB5_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b64 v[2:3], off, s[0:3], 0 offset:4 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[0:1]
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB5_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%id.zext = zext i32 %id to i64
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br label %bb1
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bb1:
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%load = call i64 @llvm.amdgcn.raw.ptr.atomic.buffer.load.i64(ptr addrspace(8) %ptr, i32 4, i32 0, i32 1)
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%cmp = icmp eq i64 %load, %id.zext
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v2i16(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_v2i16:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB6_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b32 v1, off, s[0:3], 0 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB6_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call <2 x i16> @llvm.amdgcn.raw.ptr.atomic.buffer.load.v2i16(ptr addrspace(8) %ptr, i32 0, i32 0, i32 1)
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%bitcast = bitcast <2 x i16> %load to i32
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%cmp = icmp eq i32 %bitcast, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %ptr) {
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; CHECK-SDAG-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
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; CHECK-SDAG-TRUE16: ; %bb.0: ; %bb
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; CHECK-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-SDAG-TRUE16-NEXT: s_mov_b32 s4, 0
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; CHECK-SDAG-TRUE16-NEXT: .LBB7_1: ; %bb1
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; CHECK-SDAG-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-SDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-SDAG-TRUE16-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
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; CHECK-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; CHECK-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
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; CHECK-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-SDAG-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
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; CHECK-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-SDAG-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-SDAG-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-SDAG-TRUE16-NEXT: s_cbranch_execnz .LBB7_1
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; CHECK-SDAG-TRUE16-NEXT: ; %bb.2: ; %bb2
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; CHECK-SDAG-TRUE16-NEXT: s_endpgm
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;
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; CHECK-FAKE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
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; CHECK-FAKE16: ; %bb.0: ; %bb
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; CHECK-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-FAKE16-NEXT: s_mov_b32 s4, 0
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; CHECK-FAKE16-NEXT: .LBB7_1: ; %bb1
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; CHECK-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-FAKE16-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
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; CHECK-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; CHECK-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
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; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
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; CHECK-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-FAKE16-NEXT: s_cbranch_execnz .LBB7_1
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; CHECK-FAKE16-NEXT: ; %bb.2: ; %bb2
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; CHECK-FAKE16-NEXT: s_endpgm
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;
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; CHECK-GISEL-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
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; CHECK-GISEL-TRUE16: ; %bb.0: ; %bb
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; CHECK-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-GISEL-TRUE16-NEXT: s_mov_b32 s4, 0
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; CHECK-GISEL-TRUE16-NEXT: .LBB7_1: ; %bb1
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; CHECK-GISEL-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-GISEL-TRUE16-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
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; CHECK-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; CHECK-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
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; CHECK-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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; CHECK-GISEL-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
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; CHECK-GISEL-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
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; CHECK-GISEL-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; CHECK-GISEL-TRUE16-NEXT: s_cbranch_execnz .LBB7_1
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; CHECK-GISEL-TRUE16-NEXT: ; %bb.2: ; %bb2
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; CHECK-GISEL-TRUE16-NEXT: s_endpgm
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1:
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%load = call <4 x i16> @llvm.amdgcn.raw.ptr.atomic.buffer.load.v4i16(ptr addrspace(8) %ptr, i32 4, i32 0, i32 1)
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%shortened = shufflevector <4 x i16> %load, <4 x i16> poison, <2 x i32> <i32 0, i32 2>
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%bitcast = bitcast <2 x i16> %shortened to i32
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%cmp = icmp eq i32 %bitcast, %id
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br i1 %cmp, label %bb1, label %bb2
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bb2:
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ret void
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}
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define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i32(ptr addrspace(8) %ptr) {
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; CHECK-LABEL: raw_ptr_atomic_buffer_load_v4i32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: .LBB8_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_load_b128 v[1:4], off, s[0:3], 0 offset:4 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v4, v0
|
|
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
|
|
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
|
|
; CHECK-NEXT: s_cbranch_execnz .LBB8_1
|
|
; CHECK-NEXT: ; %bb.2: ; %bb2
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
br label %bb1
|
|
bb1:
|
|
%load = call <4 x i32> @llvm.amdgcn.raw.ptr.atomic.buffer.load.v4i32(ptr addrspace(8) %ptr, i32 4, i32 0, i32 1)
|
|
%extracted = extractelement <4 x i32> %load, i32 3
|
|
%cmp = icmp eq i32 %extracted, %id
|
|
br i1 %cmp, label %bb1, label %bb2
|
|
bb2:
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @raw_ptr_atomic_buffer_load_ptr(ptr addrspace(8) %ptr) {
|
|
; CHECK-LABEL: raw_ptr_atomic_buffer_load_ptr:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: s_mov_b32 s4, 0
|
|
; CHECK-NEXT: .LBB9_1: ; %bb1
|
|
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: flat_load_b32 v1, v[1:2]
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v0
|
|
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
|
|
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; CHECK-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
|
|
; CHECK-NEXT: s_cbranch_execnz .LBB9_1
|
|
; CHECK-NEXT: ; %bb.2: ; %bb2
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
br label %bb1
|
|
bb1:
|
|
%load = call ptr @llvm.amdgcn.raw.ptr.atomic.buffer.load.ptr(ptr addrspace(8) %ptr, i32 4, i32 0, i32 1)
|
|
%elem = load i32, ptr %load
|
|
%cmp = icmp eq i32 %elem, %id
|
|
br i1 %cmp, label %bb1, label %bb2
|
|
bb2:
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: nounwind readonly
|
|
declare i32 @llvm.amdgcn.raw.ptr.atom.buffer.load.i32(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare i64 @llvm.amdgcn.raw.ptr.atom.buffer.load.i64(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare <2 x i16> @llvm.amdgcn.raw.ptr.atom.buffer.load.v2i16(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare <4 x i16> @llvm.amdgcn.raw.ptr.atom.buffer.load.v4i16(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare <4 x i32> @llvm.amdgcn.raw.ptr.atom.buffer.load.v4i32(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare ptr @llvm.amdgcn.raw.ptr.atom.buffer.load.ptr(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8), i32, i32, i32 immarg)
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|