9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=TONGA %s
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; On Tonga and Iceland, limited SGPR availability means care must be taken to
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; allocate scratch registers correctly. Check that this test compiles without
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; error.
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; TONGA-LABEL: test
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define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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entry:
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%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
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%aptr = getelementptr <256 x i32>, ptr addrspace(1) %in, i32 %tid
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%a = load <256 x i32>, ptr addrspace(1) %aptr
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call void asm sideeffect "", "~{memory}" ()
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%outptr = getelementptr <256 x i32>, ptr addrspace(1) %in, i32 %tid
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store <256 x i32> %a, ptr addrspace(1) %outptr
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; mark 128-bit SGPR registers as used so they are unavailable for the
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; scratch resource descriptor
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call void asm sideeffect "", "~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28}" ()
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call void asm sideeffect "", "~{s32},~{s36},~{s40},~{s44},~{s48},~{s52},~{s56}" ()
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call void asm sideeffect "", "~{s60},~{s64},~{s68}" ()
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
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attributes #0 = { nounwind readnone }
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