9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
62 lines
2.9 KiB
LLVM
62 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-TFILD %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -combiner-tokenfactor-inline-limit=7 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-TFIL7 %s
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; GCN-LABEL: {{^}}token_factor_inline_limit_test:
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; GCN-TFLID: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
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; GCN-TFLID: buffer_store_dword [[REG7]], {{.*$}}
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; GCN-TFILD: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
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; GCN-TFILD: buffer_store_dword [[REG8]], {{.*}} offset:4
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; GCN-TFILD: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
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; GCN-TFILD: buffer_store_dword [[REG9]], {{.*}} offset:8
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; GCN-TFILD: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
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; GCN-TFILD: buffer_store_dword [[REG10]], {{.*}} offset:12
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; GCN-TFILD: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
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; GCN-TFILD: buffer_store_dword [[REG11]], {{.*}} offset:16
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; GCN-TFILD: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
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; GCN-TFILD: buffer_store_dword [[REG12]], {{.*}} offset:20
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; GCN-TFILD: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
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; GCN-TFILD: buffer_store_dword [[REG13]], {{.*}} offset:24
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; GCN-TFILD: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
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; GCN-TFILD: buffer_store_dword [[REG14]], {{.*}} offset:28
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; GCN-TFILD: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
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; GCN-TFILD: buffer_store_dword [[REG15]], {{.*}} offset:32
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; GCN-TFIL7: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
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; GCN-TFIL7: buffer_store_dword [[REG15]], {{.*}} offset:32
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; GCN-TFIL7: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
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; GCN-TFIL7: buffer_store_dword [[REG14]], {{.*}} offset:28
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; GCN-TFIL7: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
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; GCN-TFIL7: buffer_store_dword [[REG13]], {{.*}} offset:24
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; GCN-TFIL7: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
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; GCN-TFIL7: buffer_store_dword [[REG12]], {{.*}} offset:20
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; GCN-TFIL7: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
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; GCN-TFIL7: buffer_store_dword [[REG11]], {{.*}} offset:16
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; GCN-TFIL7: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
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; GCN-TFIL7: buffer_store_dword [[REG10]], {{.*}} offset:12
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; GCN-TFIL7: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
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; GCN-TFIL7: buffer_store_dword [[REG9]], {{.*}} offset:8
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; GCN-TFIL7: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
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; GCN-TFIL7: buffer_store_dword [[REG8]], {{.*}} offset:4
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; GCN-TFLL7: v_mov_b32_e32 [[REG7:v[0-9]+]], 7
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; GCN-TFLL7: buffer_store_dword [[REG7]], {{.*$}}
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; GCN: s_getpc
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define void @token_factor_inline_limit_test() {
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entry:
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call void @external_void_func_8xv5i32(
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<5 x i32><i32 0, i32 0, i32 0, i32 0, i32 0>,
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<5 x i32><i32 1, i32 1, i32 1, i32 1, i32 1>,
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<5 x i32><i32 2, i32 2, i32 2, i32 2, i32 2>,
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<5 x i32><i32 3, i32 3, i32 3, i32 3, i32 3>,
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<5 x i32><i32 4, i32 4, i32 4, i32 4, i32 4>,
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<5 x i32><i32 5, i32 5, i32 5, i32 5, i32 5>,
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<5 x i32><i32 6, i32 7, i32 8, i32 9, i32 10>,
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<5 x i32><i32 11, i32 12, i32 13, i32 14, i32 15>)
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ret void
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}
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declare hidden void @external_void_func_8xv5i32(<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>,
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<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>)
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