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llvm-project/llvm/lib/Target/RISCV
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Philip Reames 3df27e9741 [RISCV] Minor style cleanup in advance of D141311 [nfc]
2023-01-09 11:31:54 -08:00
..
AsmParser
[Support] Move TargetParsers to new component
2022-12-20 11:05:50 +00:00
Disassembler
[RISCV] Implement assembler support for XTHeadVdot
2022-12-26 19:05:22 +08:00
GISel
[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
2022-11-15 14:24:50 -08:00
MCA
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
2022-11-18 09:55:15 -08:00
MCTargetDesc
[RISCV] Use tail agnostic if inserting subvector/element at the end of a vector.
2022-12-31 11:29:09 +08:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
RISCV.h
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
RISCV.td
[RISCV] Add Svpbmt extension support.
2022-12-28 23:57:54 -08:00
RISCVAsmPrinter.cpp
[RISCV] Minor style cleanup in advance of D141311 [nfc]
2023-01-09 11:31:54 -08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add support for predicating AND/OR/XOR/ADD/SUB with short-forward-branch-opt.
2022-12-16 22:58:43 -08:00
RISCVFrameLowering.cpp
[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot
2022-12-17 11:55:34 +05:30
RISCVFrameLowering.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVGatherScatterLowering.cpp
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
2023-01-05 14:11:08 +01:00
RISCVInsertVSETVLI.cpp
[RISCV][NFC] Refine the patch of D141061
2023-01-06 00:48:24 +08:00
RISCVInstrFormats.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
2023-01-05 14:11:08 +01:00
RISCVInstrInfo.h
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVInstrInfo.td
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
2022-12-28 19:59:42 -08:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
Add MC support of RISCV Zcd Extension
2022-11-24 05:48:06 +08:00
RISCVInstrInfoD.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoF.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions
2022-12-06 16:57:35 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
RISCVInstrInfoVSDPatterns.td
[DAGCombiner] Scalarize extend/truncate for splat vector.
2022-12-12 14:53:10 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Rename SDT_RISCVVecCvtX2FOp_VL->SDT_RISCVVecCvtF2XOp_VL. NFC
2023-01-05 16:37:13 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Implement assembler support for XTHeadVdot
2022-12-26 19:05:22 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Add more XVentanaCondOps patterns.
2023-01-06 08:29:23 -08:00
RISCVInstrInfoZb.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoZfh.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
2022-12-14 11:52:01 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X).
2022-12-29 16:33:18 -08:00
RISCVISelDAGToDAG.h
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
2022-12-28 19:59:42 -08:00
RISCVISelLowering.cpp
[NFC] Hide implementation details in anonymous namespaces
2023-01-08 17:37:02 +01:00
RISCVISelLowering.h
[RISCV] Use vfirst.m to extract the first element from mask vector.
2023-01-03 11:24:18 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Reduce duplicated code in RISCVMergeBaseOffsetOpt::detectFoldable. NFC
2022-12-20 07:16:43 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.td
[RISCV][NFC] Define variables for vector VT list of different LMUL
2022-12-12 10:45:30 +08:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVSchedule.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVScheduleV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions
2022-12-06 16:57:35 -08:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVStripWSuffix.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVSubtarget.cpp
[RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine.
2022-12-20 11:55:33 -08:00
RISCVSubtarget.h
[RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine.
2022-12-20 11:55:33 -08:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Add support for the vscale_range attribute.
2023-01-06 08:20:37 -08:00
RISCVTargetMachine.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Add half type support for the cost model of sqrt/fabs
2023-01-09 12:57:03 +08:00
RISCVTargetTransformInfo.h
[SLP]Fix cost of the broadcast buildvector/gather.
2023-01-06 09:25:05 -08:00