Craig Topper 05e2ee9664

[RISCV] Replace riscv.clmul intrinsic with llvm.clmul (#178092) ...

I did not replace riscv.clmulh/clmulr since those require a multiple
instruction pattern match. I wanted to ensure that -O0 will select the
correct instructions without relying on combines.

2026-01-26 21:12:48 -08:00

..

AArch64

[HWASan] [MTE] allow lifetimes with multiple starts (#175608)

2026-01-26 19:47:49 +00:00

AMDGPU

[AMDGPU] Pre-GFX10 does not need added latency for workgroup fences (#177157)

2026-01-27 10:24:05 +09:00

ARC

…

ARM

[SDAG] Remove non-canonical fabs libcall handling (#177967)

2026-01-26 15:11:17 +00:00

AVR

IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)

2026-01-21 09:50:28 +00:00

BPF

…

CSKY

[CSKY] Use softPromoteHalfType (#175138)

2026-01-09 11:10:54 +01:00

DirectX

[HLSL] Implement f32tof16() intrinsic (#172469)

2026-01-26 15:06:48 +00:00

Generic

[TargetLowering] Change the softPromoteHalfType default to true (#175149)

2026-01-11 12:48:26 +01:00

Hexagon

[SDAG] Remove non-canonical fabs libcall handling (#177967)

2026-01-26 15:11:17 +00:00

Inputs

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Lanai

…

LoongArch

[LoongArch] Remove DAG combination for extractelement (#177083)

2026-01-21 14:42:17 +08:00

M68k

[M68k] Update llvm/test/CodeGen/M68k/pipeline.ll (#177910)

2026-01-26 09:22:31 +00:00

Mips

[SDAG] Remove non-canonical fabs libcall handling (#177967)

2026-01-26 15:11:17 +00:00

MIR

[AMDGPU] Improve crash message when S_WAITCNT_DEPCTR is missing its operand (#177065)

2026-01-26 08:35:30 -08:00

MIR2Vec

[win][x64] Unwind v2: Avoid non-terminator instructions after terminator by using different psuedo for splitting frame infos (#177007)

2026-01-21 12:28:23 -08:00

MLRegAlloc

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MSP430

[MSP430] Use softPromoteHalfType (#175139)

2026-01-09 11:08:34 +01:00

NVPTX

Revert "[NVPTX] Weak cmpxchg unittests for NVPTX" (#178090)

2026-01-26 17:52:49 -08:00

PowerPC

[SDAG] Remove non-canonical fabs libcall handling (#177967)

2026-01-26 15:11:17 +00:00

RISCV

[RISCV] Replace riscv.clmul intrinsic with llvm.clmul (#178092)

2026-01-26 21:12:48 -08:00

SPARC

IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)

2026-01-21 09:50:28 +00:00

SPIRV

[HLSL] Implement f32tof16() intrinsic (#172469)

2026-01-26 15:06:48 +00:00

SystemZ

[SystemZ] Support fp16 vector ABI and basic codegen. (#171066)

2026-01-26 13:42:25 -06:00

Thumb

[CodeGen] Consider imm offsets when sorting framerefs (#171012)

2026-01-08 17:48:30 -05:00

Thumb2

IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)

2026-01-21 09:50:28 +00:00

VE

IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)

2026-01-21 09:50:28 +00:00

WebAssembly

TargetLowering: Allow FMINNUM/FMAXNUM to lower to FMINIMUM/FMAXIMUM even without nsz (#177828)

2026-01-25 18:24:12 -05:00

WinCFGuard

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WinEH

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X86

[SDAG] Remove non-canonical fabs libcall handling (#177967)

2026-01-26 15:11:17 +00:00

XCore

[XCore] Use softPromoteHalfType (#175142)

2026-01-09 10:31:01 +00:00

Xtensa

[Xtensa] Regenerate test/CodeGen/Xtensa/mul.ll to fix test

2026-01-08 22:13:20 -08:00