Craig Topper abc1acf8df
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
If the upper bits of the shr aren't demanded.

This helps with cases where the outer srl was originally an sra and was
converted to a srl by SimplifyDemandedBits before it had a chance to
combine with the inner sra. This can occur when the inner sra was part
of a sign_extend_inreg expansion.

There are some regressions in ARM and Thumb2.
2024-08-14 08:44:57 -07:00
..
2022-10-11 17:24:06 +00:00
2023-09-01 19:45:03 -04:00
2023-02-14 10:25:24 -04:00
2022-10-11 17:24:06 +00:00
2023-06-28 14:50:16 -04:00
2022-10-11 17:24:06 +00:00
2022-10-11 17:24:06 +00:00
2022-11-04 10:18:04 -07:00