Nemanja Ivanovic 0765f6451f

[RISCV] Use correct register class for Z[df]inx inline asm (#71872) ...

Allocate a register of the correct register class for inline asm
constraint "r" when used for FP values with -Zfinx/-Zdinx.

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Co-authored-by: Nemanja Ivanovic <nemanja@synopsys.com>

2023-11-17 16:17:48 +01:00

..

AArch64

Revert "[MachineSink][AArch64] Enable sink-and-fold by default (#72132)"

2023-11-16 17:07:39 +00:00

AMDGPU

[AMDGPU] - Add constant folding for s_quadmask (#72381)

2023-11-17 15:24:23 +01:00

ARC

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ARM

[SDAG] Simplify is-power-of-2 codegen (#72275)

2023-11-15 22:26:34 +09:00

AVR

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

BPF

[SCEV] Extend isImpliedCondOperandsViaRanges to independent predicates (#71110)

2023-11-07 07:25:47 -08:00

CSKY

[CSKY,test] Update switch.ll

2023-10-31 15:47:05 -07:00

DirectX

[DirectX] Update test after opt learned to infer datalayout (#70726)

2023-10-30 14:04:15 -07:00

Generic

[CodeGen][AArch64] Set min jump table entries to 13 for AArch64 targets (#71166)

2023-11-14 13:00:28 +00:00

Hexagon

[MachineLICM] Allow hoisting loads from invariant address (#70796)

2023-11-16 11:12:10 +00:00

Inputs

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Lanai

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LoongArch

[LoongArch] Improve codegen for atomic cmpxchg ops (#69339)

2023-10-19 09:21:51 +08:00

M68k

[GlobalISel][M68k] Update test after 373c343

2023-11-02 03:32:47 +01:00

Mips

[MachineLICM] Allow hoisting loads from invariant address (#70796)

2023-11-16 11:12:10 +00:00

MIR

[X86] Support EGPR (R16-R31) for APX (#70958)

2023-11-09 23:39:40 +08:00

MLRegAlloc

Fix error message when regalloc eviction advisor analysis could not be created (#72165)

2023-11-14 11:17:17 -08:00

MSP430

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

NVPTX

[NVPTX] split long-running wmma.py test into smaller chunks. (#72331)

2023-11-15 09:55:47 -08:00

PowerPC

[PowerPC] Forbid f128 SELECT_CC optimized into fsel (#71497)

2023-11-15 12:20:06 +08:00

RISCV

[RISCV] Use correct register class for Z[df]inx inline asm (#71872)

2023-11-17 16:17:48 +01:00

SPARC

[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)

2023-10-10 20:34:20 +03:00

SPIRV

[SPIR-V] Emit proper pointer type for OpenCL kernel arguments (#67726)

2023-10-18 20:51:53 -07:00

SystemZ

[SystemZ] Enable AtomicExpand pass (#70398)

2023-10-31 09:51:06 +01:00

Thumb

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Thumb2

[DAG] foldABSToABD - add support for abs(sub(sign_extend_inreg(),sign_extend_inreg())) patterns

2023-11-15 15:49:30 +00:00

VE

BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads

2023-10-24 20:27:39 -07:00

WebAssembly

[IR] Remove zext and sext constant expressions (#71040)

2023-11-03 10:46:07 +01:00

WinCFGuard

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WinEH

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X86

[X86] Ensure asm comments only print the constant values for the vector load's register width

2023-11-17 14:30:30 +00:00

XCore

[RegScavenger] Simplify state tracking for backwards scavenging (#71202)

2023-11-08 09:49:07 +00:00