Craig Topper 0a42db682a [SelectionDAG] Simplify creation of getStoreVP in WidenVecOp_STORE. NFC ...

We can use the offset from the original store instead of creating
a new undef offset.

We didn't check if the offset was undef already so we really shouldn't
drop it if it isn't.

2025-05-21 17:46:08 -07:00

..

CMakeLists.txt

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358)

2025-04-06 13:14:37 +03:00

DAGCombiner.cpp

[LLVM][AArch64] Correctly lower funnel shifts by constants. (#140058)

2025-05-20 11:15:21 +01:00

FastISel.cpp

[IR] Teach getAsmString to return StringRef (NFC) (#139406)

2025-05-10 22:59:09 -07:00

FunctionLoweringInfo.cpp

[SelectionDAG] Use Register and MCRegister. NFC

2025-03-02 22:33:25 -08:00

InstrEmitter.cpp

[CodeGen] Use llvm::append_range (NFC) (#133603)

2025-03-29 16:53:02 -07:00

InstrEmitter.h

[NFC] Reapply 3f37c517f, SmallDenseMap speedups

2024-09-26 10:49:29 +01:00

LegalizeDAG.cpp

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)

2025-05-16 09:37:02 -07:00

LegalizeFloatTypes.cpp

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)

2025-05-16 09:37:02 -07:00

LegalizeIntegerTypes.cpp

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)

2025-05-16 09:37:02 -07:00

LegalizeTypes.cpp

[CodeGen] Use llvm::append_range (NFC) (#135567)

2025-04-13 16:36:03 -07:00

LegalizeTypes.h

[SelectionDAG] Add an ISD node for for get.active.lane.mask (#139084)

2025-05-15 09:14:46 +01:00

LegalizeTypesGeneric.cpp

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)

2025-05-16 09:37:02 -07:00

LegalizeVectorOps.cpp

[DAG/RISCV] Continue mitgrating to getInsertSubvector and getExtractSubvector

2025-05-08 09:40:45 -07:00

LegalizeVectorTypes.cpp

[SelectionDAG] Simplify creation of getStoreVP in WidenVecOp_STORE. NFC

2025-05-21 17:46:08 -07:00

MatchContext.h

[DAG][RISCV] Use vp.<binop> when widening illegal types for binops which can trap (#105214)

2024-08-20 13:51:10 -07:00

ResourcePriorityQueue.cpp

…

ScheduleDAGFast.cpp

[CodeGen] Use range-based for loops (NFC) (#138488)

2025-05-05 10:08:49 -07:00

ScheduleDAGRRList.cpp

[SelectionDAG] Use Register and MCRegister. NFC

2025-03-02 22:33:25 -08:00

ScheduleDAGSDNodes.cpp

[SelectionDAG] Use Register and MCRegister. NFC

2025-03-02 22:33:25 -08:00

ScheduleDAGSDNodes.h

[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)

2025-01-23 09:16:09 +00:00

ScheduleDAGVLIW.cpp

[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)

2025-01-23 09:16:09 +00:00

SDNodeDbgValue.h

[llvm] Use llvm::copy (NFC) (#137470)

2025-04-26 15:50:38 -07:00

SDNodeInfo.cpp

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358)

2025-04-06 13:14:37 +03:00

SelectionDAG.cpp

[SDAG] Ensure load is included in output chain of sincos expansion (#140525)

2025-05-20 10:43:50 +01:00

SelectionDAGAddressAnalysis.cpp

…

SelectionDAGBuilder.cpp

[AMDGPU] Set AS8 address width to 48 bits

2025-05-19 17:26:05 -07:00

SelectionDAGBuilder.h

[SelectionDAG] Use Register and MCRegister. NFC

2025-03-02 22:33:25 -08:00

SelectionDAGDumper.cpp

[SelectionDAG] Add an ISD node for for get.active.lane.mask (#139084)

2025-05-15 09:14:46 +01:00

SelectionDAGISel.cpp

CodeGen: Add ISD::AssertNoFPClass (#138839)

2025-05-15 16:05:15 +08:00

SelectionDAGPrinter.cpp

[llvm][CodeGen] Avoid 'raw_string_ostream::str' (NFC) (#97318)

2024-07-01 21:52:37 -04:00

SelectionDAGTargetInfo.cpp

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358)

2025-04-06 13:14:37 +03:00

StatepointLowering.cpp

[CodeGen] Avoid repeated hash lookups (NFC) (#131722)

2025-03-18 00:26:59 -07:00

StatepointLowering.h

…

TargetLowering.cpp

[TargetLowering] Use getExtractSubvector/getExtractVectorElt. NFC

2025-05-21 12:06:54 -07:00