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llvm-project/llvm/lib/Target/AMDGPU
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Daniil Fukalov ab05ab59a7 [CostModel][AMDGPU] Fix instructions costs estimation for vector types. 
1. Fixed vector instructions costs estimations incosistency - removed different
   logic for "not simple types" since it biases costs for these types.
2. Fixed legalization penalty for vectors too big for the target: changed from
   overwrite default legalization cost value estimation to added penalty.
3. Fixed few typos in tests.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D114893
2021-12-03 03:08:08 +03:00
..
AsmParser
[AMDGPU] Support shared literals in FMAMK/FMAAK
2021-10-11 13:09:54 -04:00
Disassembler
[AMDGPU] Support shared literals in FMAMK/FMAAK
2021-10-11 13:09:54 -04:00
MCA
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
MCTargetDesc
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[AMDGPU] Make vector superclasses allocatable
2021-11-26 00:42:12 -05:00
AMDGPU.h
[AMDGPU] Promote generic pointer kernel arguments into global
2021-10-12 10:07:33 -07:00
AMDGPU.td
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUAliasAnalysis.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUAliasAnalysis.h
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUAlwaysInlinePass.cpp
[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
2021-10-18 16:53:15 -06:00
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
2021-09-20 14:48:50 -07:00
AMDGPUAnnotateUniformValues.cpp
[OpaquePtr] Clean up some uses of Type::getPointerElementType()
2021-05-31 09:54:57 -07:00
AMDGPUArgumentUsageInfo.cpp
[GlobalISel] NFC: Change LLT::vector to take ElementCount.
2021-06-24 11:26:12 +01:00
AMDGPUArgumentUsageInfo.h
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
AMDGPUAsmPrinter.cpp
AMDGPU: Account for implicit argument alignment for kernarg segment
2021-11-09 17:48:37 -05:00
AMDGPUAsmPrinter.h
[AMDGPU] Remove unused declaration findNumUsedRegistersSI (NFC)
2021-10-27 21:24:02 -07:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
2021-09-20 14:48:50 -07:00
AMDGPUAttributor.cpp
AMDGPU: Sanitized functions require implicit arguments
2021-12-02 17:55:43 -05:00
AMDGPUCallingConv.td
[AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values.
2021-11-04 21:50:18 +01:00
AMDGPUCallLowering.cpp
[AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values.
2021-11-04 21:50:18 +01:00
AMDGPUCallLowering.h
AMDGPU/GlobalISel: Redo kernel argument load handling
2021-07-16 08:56:54 -04:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Change numBitsSigned for simplicity and document it. NFC.
2021-10-29 14:22:06 +01:00
AMDGPUCombine.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
AMDGPUCombinerHelper.cpp
Fix MSVC signed/unsigned mismatch warning. NFC.
2021-11-17 18:59:23 +00:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUCtorDtorLowering.cpp
[amdgpu] Don't crash on empty global ctor/dtor
2021-11-16 14:36:08 +00:00
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
AMDGPUFixFunctionBitcasts.cpp
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
[AMDGPU][GlobalISel] Add G_AMDGPU_FFBL_B32
2021-08-06 09:40:48 +01:00
AMDGPUGlobalISelUtils.cpp
…
AMDGPUGlobalISelUtils.h
[ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC)
2021-06-03 18:34:36 +02:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Account for implicit argument alignment for kernarg segment
2021-11-09 17:48:37 -05:00
AMDGPUHSAMetadataStreamer.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
AMDGPUInstCombineIntrinsic.cpp
[llvm] Migrate from arg_operands to args (NFC)
2021-09-30 08:51:21 -07:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUInstrInfo.td
[AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values.
2021-11-04 21:50:18 +01:00
AMDGPUInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
AMDGPUInstructionSelector.cpp
[AMDGPU] Check for unneeded shift mask in shift PatFrags.
2021-11-24 10:53:12 +05:30
AMDGPUInstructionSelector.h
[AMDGPU] Check for unneeded shift mask in shift PatFrags.
2021-11-24 10:53:12 +05:30
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPUISelLowering.cpp
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPUISelLowering.h
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPULateCodeGenPrepare.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULegalizerInfo.cpp
[AMDGPU] Simplify 64-bit division/remainder expansion
2021-11-12 15:48:41 +00:00
AMDGPULegalizerInfo.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPULibCalls.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPULibFunc.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPULibFunc.h
…
AMDGPULowerIntrinsics.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULowerKernelArguments.cpp
[NFC] More get/removeAttribute() cleanup
2021-08-17 21:05:41 -07:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
2021-07-06 15:03:31 -07:00
AMDGPULowerModuleLDSPass.cpp
[AMDGPU] Correctly merge alias.scope and noalias metadata for memops
2021-09-21 13:02:01 -05:00
AMDGPUMachineCFGStructurizer.cpp
[CodeGen, Target] Use MachineRegisterInfo::use_operands (NFC)
2021-11-11 22:28:55 -08:00
AMDGPUMachineFunction.cpp
[AMDGPU] Fix module LDS selection
2021-05-20 15:59:01 -07:00
AMDGPUMachineFunction.h
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[NFC][llvm] Inclusive language: reword and remove uses of sanity in llvm/lib/Target
2021-11-17 21:59:00 -05:00
AMDGPUMCInstLower.h
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUPerfHintAnalysis.cpp
[AMDGPU] Tune perfhint analysis to account access width
2021-07-21 12:46:10 -07:00
AMDGPUPerfHintAnalysis.h
[AMDGPU] Tune perfhint analysis to account access width
2021-07-21 12:46:10 -07:00
AMDGPUPostLegalizerCombiner.cpp
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
AMDGPUPreLegalizerCombiner.cpp
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUPrintfRuntimeBinding.cpp
[llvm] Use range-based for loops (NFC)
2021-12-02 09:27:47 -08:00
AMDGPUPromoteAlloca.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUPromoteKernelArguments.cpp
[AMDGPU] Promote generic pointer kernel arguments into global
2021-10-12 10:07:33 -07:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Use attributor to propagate amdgpu-flat-work-group-size
2021-10-22 16:23:50 -04:00
AMDGPUPTNote.h
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Fix constant bus restriction errors for med3
2021-12-01 21:36:37 +01:00
AMDGPURegisterBankInfo.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
AMDGPURegisterBankInfo.h
[AMDGPU] Remove selectStoreIntrinsic (NFC)
2021-11-14 19:40:44 -08:00
AMDGPURegisterBanks.td
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
AMDGPUReplaceLDSUseWithPointer.cpp
Use llvm::erase_if (NFC)
2021-10-18 09:33:42 -07:00
AMDGPUResourceUsageAnalysis.cpp
AMDGPU: Report large stack usage for recursive calls
2021-11-10 20:02:01 -05:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] Set number vgprs used in PS shaders based on input registers actually used
2021-10-08 14:24:35 +01:00
AMDGPURewriteOutArguments.cpp
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
2021-09-20 14:48:50 -07:00
AMDGPUSearchableTables.td
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
AMDGPUSubtarget.cpp
AMDGPU: Account for implicit argument alignment for kernarg segment
2021-11-09 17:48:37 -05:00
AMDGPUSubtarget.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUTargetMachine.cpp
[InferAddressSpaces] Support assumed addrspaces from addrspace predicates.
2021-11-08 16:51:57 -05:00
AMDGPUTargetMachine.h
[InferAddressSpaces] Support assumed addrspaces from addrspace predicates.
2021-11-08 16:51:57 -05:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[CostModel][AMDGPU] Fix instructions costs estimation for vector types.
2021-12-03 03:08:08 +03:00
AMDGPUTargetTransformInfo.h
[Target][CodeGen] Remove default CostKind arguments on inner/impl TTI overrides
2021-09-22 15:28:08 +01:00
AMDGPUUnifyDivergentExitNodes.cpp
[Analysis, Target, Transforms] Construct SmallVector with iterator ranges (NFC)
2021-09-07 09:19:33 -07:00
AMDGPUUnifyMetadata.cpp
…
AMDILCFGStructurizer.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU] Fix upcoming TableGen warnings on unused template arguments. NFC.
2021-09-16 09:07:18 +01:00
CaymanInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
CMakeLists.txt
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
DSInstructions.td
[AMDGPU] Add patterns for i8/i16 local atomic load/store
2021-10-18 11:23:10 +02:00
EvergreenInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
EXPInstructions.td
…
FLATInstructions.td
[AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*
2021-11-15 12:51:12 +03:00
GCNDPPCombine.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
GCNHazardRecognizer.cpp
[AMDGPU] Remove a no-op check in the gfx90a hazard recognizer
2021-11-23 15:35:19 -08:00
GCNHazardRecognizer.h
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
2021-06-14 22:30:23 +02:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNNSAReassign.cpp
…
GCNPreRAOptimizations.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNProcessors.td
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
GCNRegPressure.cpp
[AMDGPU] Make vector superclasses allocatable
2021-11-26 00:42:12 -05:00
GCNRegPressure.h
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
GCNSchedStrategy.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNSchedStrategy.h
[AMDGPU] NFC: Fixing small spelling errors in AMDGPU header files
2021-09-16 13:03:09 -07:00
GCNSubtarget.h
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
InstCombineTables.td
…
MIMGInstructions.td
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600.td
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600AsmPrinter.cpp
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600ControlFlowFinalizer.cpp
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600ExpandSpecialInstrs.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600InstrInfo.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600InstrInfo.td
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600Instructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
R600ISelDAGToDAG.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600ISelLowering.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
R600ISelLowering.h
Change TargetLowering::canMergeStoresTo() to take a MF instead of DAG.
2021-08-06 12:57:53 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[llvm] Use range-based for loops (NFC)
2021-11-28 18:14:49 -08:00
R600MachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600MCInstLower.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600OpenCLImageTypeLoweringPass.cpp
[NFC][llvm] Inclusive language: reword and remove uses of sanity in llvm/lib/Target
2021-11-17 21:59:00 -05:00
R600OptimizeVectorRegisters.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600Packetizer.cpp
[llvm] Use make_early_inc_range (NFC)
2021-11-21 19:24:17 -08:00
R600Processors.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
R600RegisterInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600Subtarget.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600TargetMachine.cpp
Remove the verifyAfter mechanism that was replaced by D111397
2021-10-18 10:26:46 +01:00
R600TargetMachine.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600TargetTransformInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600TargetTransformInfo.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU] Set LoopInfo as preserved by SIAnnotateControlFlow
2021-07-08 09:34:43 -07:00
SIDefines.h
[AMDGPU] Add a regclass flag for scalar registers
2021-12-01 23:31:07 -05:00
SIFixSGPRCopies.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Make vector superclasses allocatable
2021-11-26 00:42:12 -05:00
SIFormMemoryClauses.cpp
[AMDGPU][NFC] Fix typos in SIFormMemoryClauses description
2021-05-06 07:47:39 -07:00
SIFrameLowering.cpp
PrologEpilogInserter: Use explicit control for scavenge slot placement
2021-11-23 18:01:12 -05:00
SIFrameLowering.h
PrologEpilogInserter: Use explicit control for scavenge slot placement
2021-11-23 18:01:12 -05:00
SIInsertHardClauses.cpp
[AMDGPU] Ignore KILLs when forming clauses
2021-09-27 16:33:52 +02:00
SIInsertWaitcnts.cpp
[AMDGPU] Add support for in-order bvh in waitcnt pass
2021-12-02 14:26:11 +00:00
SIInstrFormats.td
[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global
2021-04-09 11:20:31 +02:00
SIInstrInfo.cpp
[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc
2021-11-29 22:19:33 -05:00
SIInstrInfo.h
[CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress
2021-11-17 10:16:47 +00:00
SIInstrInfo.td
[AMDGPU] Only select VOP3 forms of VOP2 instructions
2021-11-24 11:15:30 +00:00
SIInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
SIISelLowering.cpp
[CostModel][AMDGPU] Fix instructions costs estimation for vector types.
2021-12-03 03:08:08 +03:00
SIISelLowering.h
[AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
2021-11-29 16:27:21 +01:00
SILateBranchLowering.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
SILoadStoreOptimizer.cpp
[AMDGPU] Make vector superclasses allocatable
2021-11-26 00:42:12 -05:00
SILowerControlFlow.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SILowerI1Copies.cpp
AMDGPU: Treat IMPLICIT_DEF like a constant lanemask source
2021-07-27 11:44:38 -04:00
SILowerSGPRSpills.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMachineFunctionInfo.cpp
[AMDGPU] Fix global isel for kernels using agprs on gfx90a
2021-10-29 14:23:14 -07:00
SIMachineFunctionInfo.h
[AMDGPU] Allow to use a whole register file on gfx90a for VGPRs
2021-10-21 18:24:34 -07:00
SIMachineScheduler.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMemoryLegalizer.cpp
[AMDGPU] Add SIMemoryLegalizer comments to clarify bit usage
2021-11-26 21:05:58 +09:00
SIModeRegister.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIOptimizeExecMasking.cpp
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy
2021-03-24 14:14:13 +03:00
SIOptimizeVGPRLiveRange.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIPeepholeSDWA.cpp
[AMDGPU] Add a regclass flag for scalar registers
2021-12-01 23:31:07 -05:00
SIPostRABundler.cpp
[AMDGPU] Fix SIPostRABundler crash on null register used by dbg value
2021-11-18 17:01:19 -08:00
SIPreAllocateWWMRegs.cpp
[AMDGPU] Save WWM registers in functions
2021-04-23 18:09:24 +02:00
SIPreEmitPeephole.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
SIProgramInfo.cpp
…
SIProgramInfo.h
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
SIRegisterInfo.cpp
[AMDGPU] Enable copy between VGPR and AGPR classes during regalloc
2021-11-29 22:19:33 -05:00
SIRegisterInfo.h
[AMDGPU] Add a regclass flag for scalar registers
2021-12-01 23:31:07 -05:00
SIRegisterInfo.td
[AMDGPU] Add a regclass flag for scalar registers
2021-12-01 23:31:07 -05:00
SISchedule.td
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
SIShrinkInstructions.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIWholeQuadMode.cpp
[AMDGPU] Only allow implicit WQM in pixel shaders
2021-11-24 20:04:42 +09:00
SMInstructions.td
[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
2021-06-16 12:23:29 +01:00
SOPInstructions.td
[AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values.
2021-11-04 21:50:18 +01:00
VIInstrFormats.td
…
VOP1Instructions.td
[AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write
2021-11-19 19:00:17 +00:00
VOP2Instructions.td
[AMDGPU] Add constrained shift pattern matches.
2021-10-26 19:07:19 +05:30
VOP3Instructions.td
[AMDGPU] Add constrained shift pattern matches.
2021-10-26 19:07:19 +05:30
VOP3PInstructions.td
[AMDGPU] Add constrained shift pattern matches.
2021-10-26 19:07:19 +05:30
VOPCInstructions.td
[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
2021-06-16 13:36:02 +01:00
VOPInstructions.td
[AMDGPU] Add constrained shift pattern matches.
2021-10-26 19:07:19 +05:30