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llvm-project/llvm/test/CodeGen
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Kirill Stoimenov 021ecbbb44 [ASan] Changed intrisic implemenation to use PLT safe registers. 
Changed registers to R10 and R11 because PLT resolution clobbers them. Also changed the implementation to use R11 instead of RCX, which saves a push/pop.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D115002
2021-12-03 04:06:30 +00:00
..
AArch64
[AArch64][SVE] Enable bf16 vector.insert
2021-12-02 12:59:19 +00:00
AMDGPU
AMDGPU: Sanitized functions require implicit arguments
2021-12-02 17:55:43 -05:00
ARC
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ARM
[ARM] Introduce i8neg and i8pos addressing modes
2021-12-02 17:10:26 +00:00
AVR
[asm] Remove explicit branch for modifier 'l'
2021-11-19 09:19:53 -05:00
BPF
BPF: Workaround InstCombine trunc+icmp => mask+icmp Optimization
2021-11-18 20:25:28 -08:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[asm] Correctly handle special names in variants
2021-11-15 15:37:09 -05:00
Hexagon
[NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity in Hexagon taget
2021-11-22 10:08:01 -05:00
Inputs
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Lanai
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M68k
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Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[DebugInfo][InstrRef][NFC] "Final" x86 test cleanup
2021-11-29 22:56:09 +00:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
[NVPTX] Add imm variants for surface and texture instructions
2021-11-10 19:05:03 +03:00
PowerPC
[PowerPC] Fix load/store selection infrastructure when load/store intrinsics are used on P10.
2021-12-02 15:59:29 -06:00
RISCV
[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
2021-12-01 11:25:28 -08:00
SPARC
[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
2021-11-14 19:59:52 +01:00
SystemZ
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
2021-11-29 19:01:59 -08:00
Thumb
[clang][ARM] PACBTI-M assembly support
2021-11-30 09:28:18 +00:00
Thumb2
[ARM] Introduce i8neg and i8pos addressing modes
2021-12-02 17:10:26 +00:00
VE
[VE][NFC] Use POSIX-compatible stream redirection
2021-12-01 17:28:57 +01:00
WebAssembly
[DAG] Create fptosi.sat from clamped fptosi
2021-11-30 15:29:14 +00:00
WinCFGuard
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WinEH
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X86
[ASan] Changed intrisic implemenation to use PLT safe registers.
2021-12-03 04:06:30 +00:00
XCore
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