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llvm-project/llvm/test/CodeGen/ARM
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David Green b8f1ccb0ac [ARM] Introduce i8neg and i8pos addressing modes 
Some instructions with i8 immediate ranges can only hold negative values
(like t2LDRHi8), only hold positive values (like t2STRT) or hold +/-
depending on the U bit (like the pre/post inc instructions. e.g
t2LDRH_POST). This patch splits the AddrModeT2_i8 into AddrModeT2_i8,
AddrModeT2_i8pos and AddrModeT2_i8neg to make this clear.

This allows us to get the offset ranges of t2LDRHi8 correct in the
load/store optimizer, fixing issues where we could end up creating
instructions with positive offsets (which may then be encoded as ldrht).

Differential Revision: https://reviews.llvm.org/D114638
2021-12-02 17:10:26 +00:00
..
GlobalISel
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
ParallelDSP
[ARM][ParallelDSP] Regenerate complex_dot_prod.ll test
2021-11-21 12:01:44 +00:00
Windows
[NFC][Codegen] Tune a few tests to not end with a naked unreachable terminator
2021-07-02 23:33:30 +03:00
2006-11-10-CycleInDAG.ll
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2007-01-19-InfiniteLoop.ll
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2007-03-07-CombinerCrash.ll
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2007-03-13-InstrSched.ll
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2007-03-21-JoinIntervalsCrash.ll
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2007-03-27-RegScavengerAssert.ll
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2007-03-30-RegScavengerAssert.ll
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2007-04-02-RegScavengerAssert.ll
[NFC][llvm] Inclusive language: replace master with main in 2007-04-02-RegScavengerAssert.ll
2021-11-22 14:41:19 -06:00
2007-04-03-PEIBug.ll
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2007-04-03-UndefinedSymbol.ll
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2007-04-30-CombinerCrash.ll
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2007-05-03-BadPostIndexedLd.ll
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2007-05-07-tailmerge-1.ll
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2007-05-09-tailmerge-2.ll
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2007-05-14-InlineAsmCstCrash.ll
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2007-05-14-RegScavengerAssert.ll
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2007-05-22-tailmerge-3.ll
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2007-05-23-BadPreIndexedStore.ll
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2007-08-15-ReuseBug.ll
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2008-02-04-LocalRegAllocBug.ll
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2008-02-29-RegAllocLocal.ll
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2008-03-05-SxtInRegBug.ll
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2008-03-07-RegScavengerAssert.ll
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2008-04-04-ScavengerAssert.ll
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2008-04-10-ScavengerAssert.ll
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2008-04-11-PHIofImpDef.ll
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2008-05-19-LiveIntervalsBug.ll
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2008-05-19-ScavengerAssert.ll
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2008-07-17-Fdiv.ll
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2008-07-24-CodeGenPrepCrash.ll
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2008-08-07-AsmPrintBug.ll
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2008-09-17-CoalescerBug.ll
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2008-11-18-ScavengerAssert.ll
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2009-02-16-SpillerBug.ll
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2009-02-22-SoftenFloatVaArg.ll
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2009-02-27-SpillerBug.ll
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2009-03-07-SpillerBug.ll
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2009-03-09-AddrModeBug.ll
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2009-04-06-AsmModifier.ll
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2009-04-08-AggregateAddr.ll
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2009-04-08-FloatUndef.ll
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2009-04-08-FREM.ll
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2009-04-09-RegScavengerAsm.ll
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2009-05-05-DAGCombineBug.ll
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2009-05-07-RegAllocLocal.ll
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2009-05-11-CodePlacementCrash.ll
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2009-05-18-InlineAsmMem.ll
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2009-06-02-ISelCrash.ll
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2009-06-04-MissingLiveIn.ll
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2009-06-15-RegScavengerAssert.ll
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2009-06-19-RegScavengerAssert.ll
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2009-06-22-CoalescerBug.ll
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2009-06-30-RegScavengerAssert2.ll
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2009-06-30-RegScavengerAssert3.ll
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2009-06-30-RegScavengerAssert4.ll
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2009-06-30-RegScavengerAssert5.ll
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2009-06-30-RegScavengerAssert.ll
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2009-07-01-CommuteBug.ll
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2009-07-09-asm-p-constraint.ll
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2009-07-18-RewriterBug.ll
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2009-07-22-ScavengerAssert.ll
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2009-07-22-SchedulerAssert.ll
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2009-07-29-VFP3Registers.ll
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2009-08-02-RegScavengerAssert-Neon.ll
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2009-08-04-RegScavengerAssert-2.ll
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2009-08-04-RegScavengerAssert.ll
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2009-08-15-RegScavenger-EarlyClobber.ll
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2009-08-15-RegScavengerAssert.ll
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2009-08-21-PostRAKill2.ll
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2009-08-21-PostRAKill3.ll
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2009-08-21-PostRAKill.ll
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2009-08-26-ScalarToVector.ll
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2009-08-27-ScalarToVector.ll
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2009-08-29-ExtractEltf32.ll
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2009-08-29-TooLongSplat.ll
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2009-08-31-LSDA-Name.ll
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2009-08-31-TwoRegShuffle.ll
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2009-09-09-AllOnes.ll
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2009-09-09-fpcmp-ole.ll
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2009-09-10-postdec.ll
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2009-09-13-InvalidSubreg.ll
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2009-09-13-InvalidSuperReg.ll
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2009-09-20-LiveIntervalsBug.ll
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2009-09-21-LiveVariablesBug.ll
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2009-09-22-LiveVariablesBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-09-24-spill-align.ll
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2009-09-27-CoalescerBug.ll
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2009-09-28-LdStOptiBug.ll
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2009-10-02-NEONSubregsBug.ll
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2009-10-16-Scope.ll
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2009-10-27-double-align.ll
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2009-10-30.ll
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2009-11-01-NeonMoves.ll
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2009-11-02-NegativeLane.ll
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2009-11-07-SubRegAsmPrinting.ll
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2009-11-13-CoalescerCrash.ll
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2009-11-13-ScavengerAssert2.ll
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2009-11-13-ScavengerAssert.ll
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2009-11-13-VRRewriterCrash.ll
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2009-11-30-LiveVariablesBug.ll
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2009-12-02-vtrn-undef.ll
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2010-03-04-eabi-fp-spill.ll
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2010-03-04-stm-undef-addr.ll
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2010-03-18-ldm-rtrn.ll
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2010-04-09-NeonSelect.ll
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2010-04-13-v2f64SplitArg.ll
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2010-04-14-SplitVector.ll
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2010-04-15-ScavengerDebugValue.ll
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2010-05-14-IllegalType.ll
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2010-05-17-FastAllocCrash.ll
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2010-05-18-LocalAllocCrash.ll
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2010-05-18-PostIndexBug.ll
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2010-05-19-Shuffles.ll
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2010-05-20-NEONSpillCrash.ll
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2010-05-21-BuildVector.ll
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2010-06-11-vmovdrr-bitcast.ll
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2010-06-21-LdStMultipleBug.ll
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2010-06-21-nondarwin-tc.ll
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2010-06-25-Thumb2ITInvalidIterator.ll
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2010-06-29-PartialRedefFastAlloc.ll
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2010-06-29-SubregImpDefs.ll
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2010-07-26-GlobalMerge.ll
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2010-08-04-EHCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-21-OptCmpBug.ll
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2010-10-25-ifcvt-ldm.ll
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2010-11-15-SpillEarlyClobber.ll
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2010-11-29-PrologueBug.ll
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2010-12-07-PEIBug.ll
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2010-12-08-tpsoft.ll
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2010-12-15-elf-lcomm.ll
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2010-12-17-LocalStackSlotCrash.ll
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2011-01-19-MergedGlobalDbg.ll
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2011-02-04-AntidepMultidef.ll
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2011-02-07-AntidepClobber.ll
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2011-03-10-DAGCombineCrash.ll
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2011-03-15-LdStMultipleBug.ll
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2011-03-23-PeepholeBug.ll
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2011-04-07-schediv.ll
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2011-04-11-MachineLICMBug.ll
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2011-04-12-AlignBug.ll
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2011-04-12-FastRegAlloc.ll
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2011-04-15-AndVFlagPeepholeBug.ll
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2011-04-15-RegisterCmpPeephole.ll
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2011-04-26-SchedTweak.ll
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2011-04-27-IfCvtBug.ll
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2011-05-04-MultipleLandingPadSuccs.ll
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2011-06-09-TailCallByVal.ll
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2011-06-16-TailCallByVal.ll
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2011-06-29-MergeGlobalsAlign.ll
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2011-07-10-GlobalMergeBug.ll
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2011-08-02-MergedGlobalDbg.ll
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2011-08-12-vmovqqqq-pseudo.ll
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2011-08-25-ldmia_ret.ll
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2011-08-29-ldr_pre_imm.ll
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2011-08-29-SchedCycle.ll
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2011-09-09-OddVectorDivision.ll
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2011-09-19-cpsr.ll
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2011-09-28-CMovCombineBug.ll
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2011-10-26-ExpandUnalignedLoadCrash.ll
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2011-10-26-memset-inline.ll
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2011-10-26-memset-with-neon.ll
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2011-11-07-PromoteVectorLoadStore.ll
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2011-11-09-BitcastVectorDouble.ll
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2011-11-09-IllegalVectorFPIntConvert.ll
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2011-11-14-EarlyClobber.ll
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2011-11-28-DAGCombineBug.ll
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2011-11-29-128bitArithmetics.ll
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2011-11-30-MergeAlignment.ll
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2011-12-14-machine-sink.ll
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2011-12-19-sjlj-clobber.ll
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2012-01-23-PostRA-LICM.ll
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2012-01-24-RegSequenceLiveRange.ll
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2012-01-26-CoalescerBug.ll
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2012-01-26-CopyPropKills.ll
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2012-02-01-CoalescerBug.ll
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2012-03-05-FPSCR-bug.ll
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2012-03-13-DAGCombineBug.ll
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2012-03-26-FoldImmBug.ll
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2012-04-02-TwoAddrInstrCrash.ll
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2012-04-10-DAGCombine.ll
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2012-04-24-SplitEHCriticalEdge.ll
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2012-05-04-vmov.ll
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2012-05-10-PreferVMOVtoVDUP32.ll
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2012-05-29-TailDupBug.ll
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2012-06-12-SchedMemLatency.ll
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2012-08-04-DtripleSpillReload.ll
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2012-08-08-legalize-unaligned.ll
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2012-08-09-neon-extload.ll
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2012-08-13-bfi.ll
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2012-08-23-legalize-vmull.ll
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2012-08-27-CopyPhysRegCrash.ll
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2012-08-30-select.ll
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2012-09-18-ARMv4ISelBug.ll
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2012-09-25-InlineAsmScalarToVectorConv2.ll
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2012-09-25-InlineAsmScalarToVectorConv.ll
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2012-10-04-AAPCS-byval-align8.ll
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2012-10-04-FixedFrame-vs-byval.ll
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2012-10-04-LDRB_POST_IMM-Crash.ll
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2012-10-18-PR14099-ByvalFrameAddress.ll
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2012-11-14-subs_carry.ll
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2013-01-21-PR14992.ll
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2013-02-27-expand-vfma.ll
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2013-04-05-Small-ByVal-Structs-PR15293.ll
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2013-04-16-AAPCS-C4-vs-VFP.ll
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2013-04-16-AAPCS-C5-vs-VFP.ll
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2013-04-18-load-overlap-PR14824.ll
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2013-04-21-AAPCS-VA-C.1.cp.ll
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2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
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2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
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2013-05-05-IfConvertBug.ll
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2013-05-07-ByteLoadSameAddress.ll
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2013-05-13-AAPCS-byval-padding2.ll
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2013-05-13-AAPCS-byval-padding.ll
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2013-05-13-DAGCombiner-undef-mask.ll
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2013-05-31-char-shift-crash.ll
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2013-06-03-ByVal-2Kbytes.ll
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2013-07-29-vector-or-combine.ll
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2013-10-11-select-stalls.ll
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2013-11-08-inline-asm-neon-array.ll
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2014-01-09-pseudo_expand_implicit_reg.ll
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2014-02-05-vfp-regs-after-stack.ll
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2014-02-21-byval-reg-split-alignment.ll
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2014-05-14-DwarfEHCrash.ll
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2014-07-18-earlyclobber-str-post.ll
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2014-08-04-muls-it.ll
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2015-01-21-thumbv4t-ldstr-opt.ll
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2016-05-01-RegScavengerAssert.ll
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2016-08-24-ARM-LDST-dbginfo-bug.ll
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2018-02-13-PR36079.ll
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a15-mla.ll
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a15-partial-update.ll
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a15-SD-dep.ll
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a15.ll
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aapcs-hfa-code.ll
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aapcs-hfa.ll
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acle-intrinsics-rot.ll
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acle-intrinsics-v5.ll
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acle-intrinsics.ll
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add-like-or.ll
[DAG] Reassociate Add with Or
2021-07-07 10:21:07 +01:00
addimm-mulimm.ll
[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)
2021-09-07 15:42:43 +08:00
addrmode.ll
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addrspacecast.ll
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addsubcarry-promotion.ll
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addsubo-legalization.ll
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adv-copy-opt.ll
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aeabi-read-tp.ll
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aggregate-padding.ll
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alias_align.ll
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alias_store.ll
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aliases.ll
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align-sp-adjustment.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
align.ll
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alloc-no-stack-realign.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
alloca-align.ll
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alloca.ll
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analyze-branch-bkpt.ll
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and-cmpz.ll
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and-load-combine.ll
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and-sext-combine.ll
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apcs-vfp.ll
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arange-ldr.ll
[MC][CodeGen] Emit constant pools earlier
2021-08-03 20:55:31 -07:00
arg-copy-elide.ll
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argaddr.ll
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arguments2.ll
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arguments3.ll
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arguments4.ll
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arguments5.ll
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arguments6.ll
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arguments7.ll
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arguments8.ll
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arguments_f64_backfill.ll
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arguments-nosplit-double.ll
NFC: I simply added CHECK-LABEL to prevent false matches in the tests.
2017-07-07 13:41:33 +00:00
arguments-nosplit-i64.ll
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arguments.ll
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arm32-round-conv.ll
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arm32-rounding.ll
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arm-abi-attr.ll
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arm-and-tst-peephole.ll
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arm-asm.ll
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arm-bf16-dotprod-intrinsics.ll
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arm-bf16-pcs.ll
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arm-eabi.ll
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arm-frame-lowering-no-terminator.ll
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arm-frameaddr.ll
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arm-half-promote.ll
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arm-insert-subvector.ll
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arm-macho-tail.ll
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arm-matmul.ll
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arm-modifier.ll
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arm-negative-stride.ll
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arm-position-independence-jump-table.ll
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arm-position-independence.ll
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arm-post-indexing-opt.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
arm-returnaddr.ll
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arm-shrink-wrapping-linux.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
arm-shrink-wrapping.ll
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arm-storebytesmerge.ll
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arm-ttype-target2.ll
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arm-vld1.ll
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arm-vlddup-update.ll
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arm-vlddup.ll
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arm-vst1.ll
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ARMLoadStoreDBG.mir
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armv4.ll
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armv8.2a-fp16-vector-intrinsics.ll
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atomic-64bit.ll
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atomic-cmp.ll
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atomic-cmpxchg.ll
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atomic-load-store.ll
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atomic-op.ll
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atomic-ops-m33.ll
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atomic-ops-v8.ll
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atomicrmw_exclusive_monitor_ints.ll
[ARM] Prevent spilling between ldrex/strex pairs
2021-05-12 09:43:21 +01:00
atomicrmw_minmax.ll
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available_externally.ll
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avoid-cpsr-rmw.ll
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bf16-convert-intrinsics.ll
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bf16-create-get-set-dup.ll
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bf16-getlane-with-fp16.ll
[ARM] Add VGETLANEu patterns for v4f16 and v8f16
2021-09-19 14:25:21 +01:00
bf16-intrinsics-ld-st.ll
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bfc.ll
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bfi-chain-cse-crash.ll
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bfi.ll
[ARM] Reassociate BFI
2021-07-01 21:08:13 +01:00
bfloat.ll
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bfx.ll
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bic.ll
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bicZext.ll
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big-endian-eh-unwind.ll
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big-endian-neon-bitconv.ll
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big-endian-neon-extend.ll
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big-endian-neon-fp16-bitconv.ll
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big-endian-neon-trunc-store.ll
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big-endian-ret-f64.ll
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big-endian-vector-callee.ll
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big-endian-vector-caller.ll
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big-endian-vmov.ll
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bit-reverse-to-rbit.ll
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bits.ll
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bool-ext-inc.ll
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branch-on-zero.ll
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bswap16.ll
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bswap-inline-asm.ll
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build-attributes-encoding.s
[ARM] emit PACBTI-M build attributes
2021-12-01 11:05:29 +00:00
build-attributes-fn-attr0.ll
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build-attributes-fn-attr1.ll
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build-attributes-fn-attr2.ll
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build-attributes-fn-attr3.ll
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build-attributes-fn-attr4.ll
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build-attributes-fn-attr5.ll
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build-attributes-fn-attr6.ll
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build-attributes-optimization-minsize.ll
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build-attributes-optimization-mixed.ll
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build-attributes-optimization-optnone.ll
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build-attributes-optimization-optsize.ll
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build-attributes-optimization.ll
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build-attributes.ll
[ARM] emit PACBTI-M build attributes
2021-12-01 11:05:29 +00:00
bx_fold.ll
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byval_load_align.ll
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byval-align.ll
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cache-intrinsic.ll
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call_nolink.ll
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call-noret-minsize.ll
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call-noret.ll
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call-tc.ll
[ARM] Make MachineVerifier more strict about terminators
2020-08-27 07:10:20 +01:00
call.ll
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carry.ll
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cbz-implicit-it-range.ll
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cfguard-checks.ll
[ARM] Allow using ';' as asm statement separator in MSVC mode
2021-08-24 11:01:49 +03:00
cfguard-module-flag.ll
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cfi-alignment.ll
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clang-section.ll
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cls.ll
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clz.ll
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cmn.ll
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cmov_fp16.ll
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cmp1-peephole-thumb.mir
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cmp2-peephole-thumb.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cmp-bool.ll
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cmp.ll
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cmpxchg-idioms.ll
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cmpxchg-O0-be.ll
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cmpxchg-O0.ll
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cmpxchg-weak.ll
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cmpxchg.mir
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert
2021-08-04 15:02:02 +01:00
cmse-clear-float-bigend.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cmse-clear-float-hard2.ll
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cmse-clear-float-hard.ll
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cmse-clear-float-mve.ll
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cmse-clear-float.ll
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cmse-clear.ll
[ARM][CMSE] Clear the secure fp-registers when using softfp abi.
2021-09-16 12:56:43 +01:00
cmse-clrm-it-block.ll
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cmse-cve-2021-35465-return.ll
[ARM] Mitigate the cve-2021-35465 security vulnurability.
2021-09-16 12:56:43 +01:00
cmse-cve-2021-35465.ll
[ARM] Mitigate the cve-2021-35465 security vulnurability.
2021-09-16 12:56:43 +01:00
cmse-errors.ll
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cmse-expand-bxns-ret.mir
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cmse-vlldm-no-reorder.ll
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cmse-vlldm-no-reorder.mir
[ARM] Mitigate the cve-2021-35465 security vulnurability.
2021-09-16 12:56:43 +01:00
cmse.ll
[ARM][CMSE] Clear the secure fp-registers when using softfp abi.
2021-09-16 12:56:43 +01:00
coalesce-dbgvalue.ll
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coalesce-subregs.ll
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code-placement.ll
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codemodel.ll
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codesize-ifcvt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coff-no-dead-strip.ll
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combine-movc-sub.ll
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combine-vmovdrr.ll
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commute-movcc.ll
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compare-call.ll
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const-load-align-thumb.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-island-crash.ll
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constant-island-movwt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-island-SOImm-limit16.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-islands-cfg.mir
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constant-islands-split-IT.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-islands.ll
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constantfp.ll
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constantpool-align.ll
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constantpool-promote-dbg.ll
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constantpool-promote-duplicate.ll
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constantpool-promote-ldrh.ll
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constantpool-promote.ll
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constants.ll
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consthoist-icmpimm.ll
[ARM] Mark <= -1 immediate constant as cheap
2021-10-03 19:30:08 +01:00
copy-by-struct-i32.ll
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copy-cpsr.ll
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copy-paired-reg.ll
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cortex-a57-misched-alu.ll
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cortex-a57-misched-basic.ll
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cortex-a57-misched-ldm-wrback.ll
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cortex-a57-misched-ldm.ll
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cortex-a57-misched-mla.mir
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cortex-a57-misched-stm-wrback.ll
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cortex-a57-misched-stm.ll
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cortex-a57-misched-vadd.ll
…
cortex-a57-misched-vfma.ll
…
cortex-a57-misched-vldm-wrback.ll
…
cortex-a57-misched-vldm.ll
…
cortex-a57-misched-vstm-wrback.ll
…
cortex-a57-misched-vstm.ll
…
cortex-a57-misched-vsub.ll
…
cortex-m7-wideops.mir
…
cortexr52-misched-basic.ll
…
crash-greedy-v6.ll
…
crash-greedy.ll
…
crash-O0.ll
…
crash-on-pow2-shufflevector.ll
[DAG] SimplifyDemandedVectorElts - attempt to handle ADD(x,x) as single use
2021-11-26 10:32:10 +00:00
crash-shufflevector.ll
…
crash.ll
…
crc32.ll
…
cse-call.ll
…
cse-flags.ll
…
cse-ldrlit.ll
…
cse-libcalls.ll
…
csr-split.ll
…
ctor_order.ll
…
ctors_dtors.ll
…
cttz_vector.ll
…
cttz.ll
…
cxx-tlscc.ll
…
dag-combine-ldst.ll
…
dagcombine-anyexttozeroext.ll
…
dagcombine-concatvector.ll
…
darwin-eabi.ll
…
darwin-tls-preserved.ll
…
darwin-tls.ll
…
data-in-code-annotations.ll
…
dbg-range-extension.mir
…
dbg-tcreturn.ll
…
dbg.ll
…
DbgValueOtherTargets.test
…
debug-frame-large-stack.ll
…
debug-frame-no-debug.ll
…
debug-frame-vararg.ll
…
debug-frame.ll
Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume."
2021-10-28 21:45:09 +02:00
debug-info-arg.ll
…
debug-info-blocks.ll
…
debug-info-branch-folding.ll
…
debug-info-d16-reg.ll
…
debug-info-no-frame.ll
…
debug-info-qreg.ll
…
debug-info-s16-reg.ll
…
debug-info-sreg2.ll
…
debug-segmented-stacks.ll
…
debuginfo-split-carryexpr.ll
…
debugtrap.ll
…
default-float-abi.ll
…
default-reloc.ll
…
demanded-bits-and.ll
…
deprecated-asm.s
…
deps-fix.ll
…
disable-fp-elim.ll
…
disable-tail-calls.ll
…
div.ll
…
divmod-eabi.ll
…
divmod-hwdiv.ll
…
divmod.ll
…
domain-conv-vmovs.ll
…
dsp-loop-indexing.ll
…
dsp-mlal.ll
…
dwarf-eh.ll
…
dwarf-frame.ll
…
dwarf-unwind.ll
…
dyn-stackalloc.ll
…
early-cfi-sections.ll
…
eh-dispcont.ll
…
eh-resume2.ll
Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume."
2021-10-28 21:45:09 +02:00
eh-resume.ll
Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume."
2021-10-28 21:45:09 +02:00
ehabi-filters.ll
…
ehabi-handlerdata-nounwind.ll
…
ehabi-handlerdata.ll
…
ehabi-no-landingpad.ll
…
ehabi-unwind.ll
…
ehabi.ll
Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume."
2021-10-28 21:45:09 +02:00
elf-lcomm-align.ll
…
emit-big-cst.ll
…
emutls1.ll
…
emutls_generic.ll
…
emutls.ll
…
execute-only-big-stack-frame.ll
…
execute-only-section.ll
…
execute-only.ll
…
expand-pseudos.ll
[test] Avoid dumping .o in source tree (expand-pseudos.ll)
2021-11-30 16:56:53 -08:00
expand-pseudos.mir
…
extload-knownzero.ll
…
extloadi1.ll
…
fabs-neon.ll
…
fabs-to-bfc.ll
…
fabss.ll
…
fadds.ll
…
fast-isel-align.ll
…
fast-isel-binary.ll
…
fast-isel-br-const.ll
…
fast-isel-br-phi.ll
…
fast-isel-call-multi-reg-return.ll
…
fast-isel-call.ll
ARM: reuse existing libcall global variable if possible.
2021-07-14 14:14:47 +01:00
fast-isel-cmp-imm.ll
…
fast-isel-conversion.ll
…
fast-isel-crash2.ll
…
fast-isel-crash.ll
…
fast-isel-deadcode.ll
…
fast-isel-ext.ll
…
fast-isel-fold.ll
…
fast-isel-frameaddr.ll
…
fast-isel-GEP-coalesce.ll
…
fast-isel-icmp.ll
…
fast-isel-indirectbr.ll
…
fast-isel-inline-asm.ll
…
fast-isel-intrinsic.ll
…
fast-isel-ldr-str-arm.ll
…
fast-isel-ldr-str-thumb-neg-index.ll
…
fast-isel-ldrh-strh-arm.ll
…
fast-isel-load-store-verify.ll
…
fast-isel-mvn.ll
…
fast-isel-pic.ll
…
fast-isel-pie.ll
…
fast-isel-pred.ll
…
fast-isel-redefinition.ll
…
fast-isel-remat-same-constant.ll
…
fast-isel-ret.ll
…
fast-isel-select.ll
…
fast-isel-shift-materialize.ll
…
fast-isel-shifter.ll
…
fast-isel-static.ll
…
fast-isel-update-valuemap-for-extract.ll
…
fast-isel-vaddd.ll
…
fast-isel-vararg.ll
…
fast-isel.ll
…
fast-tail-call.ll
…
fastcc-tailcall.ll
…
fastcc-vfp.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-thumb-litpool.ll
…
favor-low-reg-for-Osize.ll
…
fcmp-xo.ll
…
fcopysign.ll
…
fdivs.ll
…
fence-singlethread.ll
…
fixunsdfdi.ll
…
flag-crash.ll
…
float-helpers.s
…
floorf.ll
…
fmacs.ll
…
fmdrr-fmrrd.ll
…
fminmax-folds.ll
…
fmscs.ll
…
fmuls.ll
…
fnattr-trap.ll
…
fnegs.ll
DAG: Fix incorrect folding of fmul -1 to fneg
2021-09-14 21:25:02 -04:00
fnmacs.ll
…
fnmscs.ll
…
fnmul.ll
…
fnmuls.ll
…
fold-const.ll
…
fold-sext-sextload.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-stack-adjust.ll
…
fold-zext-zextload.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
formal.ll
…
fp16-args.ll
…
fp16-bitcast.ll
…
fp16-frame-lowering.ll
…
fp16-fullfp16.ll
…
fp16-fusedMAC.ll
…
fp16-insert-extract.ll
[ARM] Add VGETLANEu patterns for v4f16 and v8f16
2021-09-19 14:25:21 +01:00
fp16-instructions.ll
…
fp16-intrinsic-vector-1op.ll
…
fp16-intrinsic-vector-2op.ll
…
fp16-litpool2-arm.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp16-litpool3-arm.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp16-litpool-arm.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp16-litpool-thumb.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp16-load-store.ll
…
fp16-no-condition.ll
…
fp16-promote.ll
…
fp16-v3.ll
…
fp16-vector-argument.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
fp16-vld.ll
…
fp16-vldlane-vstlane.ll
…
fp16-vminmaxnm-safe.ll
…
fp16-vminmaxnm-vector.ll
…
fp16-vminmaxnm.ll
…
fp16.ll
…
fp_convert.ll
…
fp-arg-shuffle.ll
…
fp-fast.ll
…
fp-intrinsics.ll
…
fp-only-sp.ll
…
fp.ll
…
fparith.ll
…
fpclamptosat_vec.ll
[DAG] Add tests for fpsti.sat for various architectures. NFC
2021-11-29 21:57:13 +00:00
fpclamptosat.ll
[ARM] Teach getIntImmCostInst about the cost of saturating fp converts
2021-12-02 07:56:27 +00:00
fpcmp_ueq.ll
…
fpcmp-f64-neon-opt.ll
…
fpcmp-opt.ll
…
fpcmp.ll
…
fpconsts.ll
…
fpconv.ll
…
fpenv.ll
…
fpmem.ll
…
fpoffset_overflow.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fpow.ll
…
fpowi.ll
…
fpscr-intrinsics.ll
…
fptoi-sat-store.ll
[ARM] Add patterns for store(fptosisat(..))
2021-09-03 19:22:11 +01:00
fptoint.ll
…
fptosi-sat-scalar.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
fptoui-sat-scalar.ll
[ARM] Add VFP lowering for fptosi.sat
2021-09-03 18:11:08 +01:00
fpvcvtr.ll
…
fragmented-args-multiple-regs.ll
…
frame-register.ll
…
freeze-soften.ll
…
fsubs.ll
…
ftrunc.ll
…
func-argpassing-endian.ll
…
funnel-shift-rot.ll
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
funnel-shift.ll
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
fusedMAC.ll
…
gep-imm.ll
[ARM] Set the immediate cost of GEP operands to 0
2021-06-30 19:19:03 +01:00
gep-optimization.ll
…
ghc-tcreturn-lowered.ll
…
global-merge-1.ll
…
global-merge-addrspace.ll
…
global-merge-alignment.ll
…
global-merge-dllexport.ll
…
global-merge-external-2.ll
…
global-merge-external.ll
…
global-merge.ll
…
globals.ll
…
gnu_mcount_nc.ll
…
gpr-paired-spill-thumbinst.ll
…
gpr-paired-spill.ll
…
gv-stubs-crash.ll
…
ha-alignstack-call.ll
…
ha-alignstack.ll
…
half.ll
…
hardfloat_neon.ll
…
hello.ll
…
hfa-in-contiguous-registers.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
…
hidden-vis.ll
…
hints.ll
…
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
2021-11-29 19:01:59 -08:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
2021-11-29 19:01:59 -08:00
i1.ll
…
i64_volatile_load_store.ll
…
iabs.ll
…
icmp-shift-opt.ll
[ARM] Precommit i128 test from D111530
2021-11-08 16:08:21 +00:00
ifconv-kills.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
ifconv-regmask.ll
…
ifcvt1.ll
…
ifcvt2.ll
…
ifcvt3.ll
…
ifcvt4.ll
…
ifcvt5.ll
…
ifcvt6.ll
…
ifcvt7.ll
…
ifcvt8.ll
…
ifcvt9.ll
…
ifcvt10.ll
…
ifcvt11.ll
…
ifcvt12.ll
…
ifcvt_canFallThroughTo.mir
…
ifcvt_diamond_unanalyzable.mir
…
ifcvt_diamondSameTrueFalse.mir
…
ifcvt_forked_diamond_unanalyzable.mir
…
ifcvt_simple_bad_zero_prob_succ.mir
…
ifcvt_simple_unanalyzable.mir
…
ifcvt_triangleSameCvtNext.mir
…
ifcvt_triangleWoCvtToNextEdge.mir
…
ifcvt-branch-weight-bug.ll
…
ifcvt-branch-weight.ll
…
ifcvt-callback.ll
…
ifcvt-dead-def.ll
…
ifcvt-diamond-unanalyzable-common.mir
…
ifcvt-iter-indbr.ll
…
ifcvt-regmask-noreturn.ll
…
ifcvt-size.mir
…
illegal-bitfield-loadstore.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
illegal-vector-bitcast.ll
…
imm-peephole-arm.mir
…
imm-peephole-thumb.mir
…
imm.ll
…
immcost.ll
…
inc-of-add.ll
…
indexed-mem.ll
…
indirect-hidden.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
indirect-reg-input.ll
…
indirectbr-2.ll
…
indirectbr-3.ll
…
indirectbr.ll
…
inline-asm-clobber.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-multilevel-gep.ll
…
inline-asm-reserved-registers.ll
…
inline-diagnostics.ll
…
inlineasm2.ll
…
inlineasm3.ll
…
inlineasm4.ll
…
inlineasm-64bit.ll
…
inlineasm-error-t-toofewregs.ll
…
inlineasm-global.ll
…
inlineasm-imm-arm.ll
…
inlineasm-imm-thumb2.ll
…
inlineasm-imm-thumb.ll
…
inlineasm-ldr-pseudo.ll
…
inlineasm-operand-implicit-cast.ll
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
inlineasm-output-template.ll
…
inlineasm-switch-mode-oneway-from-arm.ll
…
inlineasm-switch-mode-oneway-from-thumb.ll
…
inlineasm-switch-mode.ll
…
inlineasm-X-allocation.ll
…
inlineasm-X-constraint.ll
…
inlineasm.ll
…
insn-sched1.ll
…
int-to-fp.ll
…
integer_insertelement.ll
…
interrupt-attr.ll
…
interval-update-remat.ll
…
interwork.ll
…
intrinsics-cmse.ll
…
intrinsics-coprocessor.ll
…
intrinsics-crypto.ll
…
intrinsics-memory-barrier.ll
…
intrinsics-overflow.ll
…
intrinsics-v8.ll
…
invalid-target.ll
…
invalidated-save-point.ll
…
invoke-donothing-assert.ll
…
ipra-exact-definition.ll
…
ipra-no-csr.ll
…
ipra-r0-returned.ll
…
ipra-reg-usage.ll
…
ipra.ll
…
isel-v8i32-crash.ll
…
ispositive.ll
…
jump-table-islands-split.ll
…
jump-table-islands.ll
…
jump-table-tbh.ll
…
jumptable-label.ll
…
krait-cpu-div-attribute.ll
…
large-stack.ll
…
large-vector.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
ldaex-stlex.ll
…
ldc2l.ll
…
ldm-base-writeback.ll
…
ldm-stm-base-materialization.ll
…
ldm-stm-i256.ll
…
ldm.ll
…
ldr_ext.ll
…
ldr_frame.ll
…
ldr_post.ll
…
ldr_pre.ll
…
ldr.ll
…
ldrcppic.ll
…
ldrd_ifcvt.ll
[IfCvt] Don't use pristine register for counting liveins for predicated instructions.
2021-07-11 14:45:54 +01:00
ldrd-memoper.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldrd.ll
…
ldrex-frame-size.ll
…
ldst-f32-2-i32.ll
…
ldstrex-m.ll
…
ldstrex.ll
…
legalize-bitcast.ll
…
legalize-fneg.ll
…
legalize-unaligned-load.ll
…
lit.local.cfg
…
litpool-licm.ll
…
llrint-conv.ll
…
llround-conv.ll
…
load_i1_select.ll
…
load_store_multiple.ll
…
load_store_opt_clobber_cpsr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
load_store_opt_kill.mir
…
load_store_opt_reg_limit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
load-address-masked.ll
…
load-arm.ll
…
load-combine-big-endian.ll
…
load-combine.ll
…
load-global2.ll
…
load-global.ll
…
load-store-flags.ll
…
load.ll
…
local-call.ll
…
log2_not_readnone.ll
…
long_shift.ll
…
long-setcc.ll
…
long.ll
…
longMAC.ll
…
loop-align-cortex-m.ll
…
loop-indexing.ll
…
loopvectorize_pr33804.ll
…
lower-vmax.ll
…
lowerMUL-newload.ll
…
lrint-conv.ll
…
lround-conv.ll
…
lsr-code-insertion.ll
…
lsr-icmp-imm.ll
…
lsr-scale-addr-mode.ll
…
lsr-setupcost.ll
…
lsr-unfolded-offset.ll
…
machine-copyprop.mir
…
machine-cse-cmp.ll
[NFC][Codegen] Tune a few tests to not end with a naked unreachable terminator
2021-07-02 23:33:30 +03:00
machine-licm.ll
…
machine-outliner-calls.mir
…
machine-outliner-cfi-1.ll
…
machine-outliner-cfi-2.ll
…
machine-outliner-cfi-3.ll
…
machine-outliner-default.mir
…
machine-outliner-lr-regsave.mir
…
machine-outliner-no-lr-save.mir
…
machine-outliner-remove-debug-instr.mir
…
machine-outliner-return-1.ll
…
machine-outliner-return-2.ll
…
machine-outliner-stack-fixup-arm.mir
…
machine-outliner-stack-fixup-thumb.mir
[ARM] Introduce i8neg and i8pos addressing modes
2021-12-02 17:10:26 +00:00
machine-outliner-stack-use.mir
…
machine-outliner-tail.ll
…
machine-outliner-thunk.ll
…
machine-outliner-unoutlinable.mir
[ARM] Add a tail-predication loop predicate register
2021-09-02 13:42:58 +01:00
machine-outliner-unsafe-registers.mir
…
machine-sink-multidef.ll
…
machine-sink-multidef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-verifier.mir
…
macho-embedded-float.ll
…
macho-extern-hidden.ll
…
macho-frame-offset.ll
…
MachO-subtypes.ll
…
macho-trap.ll
…
mature-mc-support.ll
…
mbp.ll
[MBP] findBestLoopTopHelper should exit if OldTop is not a chain header
2021-07-28 19:00:45 -07:00
mcp-dest-regs-no-dup.mir
…
mem.ll
…
memcpy-const-vol-struct.ll
…
memcpy-inline.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
memcpy-ldm-stm.ll
…
memcpy-no-inline.ll
…
memfunc.ll
[NFC][Codegen] Tune a few tests to not end with a naked unreachable terminator
2021-07-02 23:33:30 +03:00
memset-align.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
memset-inline.ll
…
MergeConsecutiveStores.ll
…
metadata-default.ll
…
metadata-short-enums.ll
…
metadata-short-wchar.ll
…
minmax.ll
…
minsize-call-cse.ll
…
minsize-imms.ll
…
minsize-litpools.ll
…
misched-copy-arm.ll
…
misched-fp-basic.ll
…
misched-fusion-aes.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
misched-fusion-lit.ll
…
misched-int-basic-thumb2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
misched-int-basic.mir
…
mls.ll
…
movc-peephole.mir
[ARM] Fix MOVCC peephole to not use an incorrect register class
2021-10-15 10:54:26 +01:00
movcc-double.ll
…
movt-movw-global.ll
…
movt.ll
…
msr-it-block.ll
…
mul_const.ll
…
mul.ll
…
mulhi.ll
…
mult-alt-generic-arm.ll
…
mvn.ll
…
naked-no-prolog.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
negate-i1.ll
…
negative-offset.ll
…
neon_arith1.ll
…
neon_cmp.ll
…
neon_div.ll
…
neon_fpconv.ll
…
neon_ld1.ll
…
neon_ld2.ll
…
neon_minmax.ll
…
neon_shift.ll
…
neon_spill.ll
…
neon_vabs.ll
…
neon_vshl_minint.ll
…
neon-copy.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
neon-dot-product.ll
…
neon-fma.ll
…
neon-spfp.ll
…
neon-v8.1a.ll
…
neon-vcadd.ll
…
neon-vmovn.ll
…
neon-vqaddsub-upgrade.ll
…
nest-register.ll
…
nnan-fsub.ll
…
no_redundant_trunc_for_cmp.ll
[Test] Regenerate some of llc test checks using auto updater
2021-10-28 16:18:30 +07:00
no-arm-mode.ll
…
no-cfi.ll
…
no-cmov2bfi.ll
…
no-fpscr-liveness.ll
Fix typo of colon to semicolon in lit tests
2021-10-09 10:03:50 +08:00
no-fpu.ll
…
no-register-coalescing-in-returnsTwice.mir
…
no-tail-call.ll
…
nomerge.ll
…
none-macho-v4t.ll
…
none-macho.ll
…
nonreserved-callframe-with-basereg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
noopt-dmb-v7.ll
…
nop_concat_vectors.ll
…
noreturn-csr-skip.mir
…
noreturn.ll
…
null-streamer.ll
…
O3-pipeline.ll
[ARM] Implement BTI placement pass for PACBTI-M
2021-12-01 12:54:05 +00:00
opt-shuff-tstore.ll
…
optimize-dmbs-v7.ll
…
optselect-regclass.ll
…
out-of-registers.ll
…
overflow-intrinsic-optimizations.ll
[ARMISelLowering] avoid emitting libcalls to __mulodi4()
2021-08-27 15:14:47 -07:00
pacbti-module-attrs.ll
[ARM] emit PACBTI-M build attributes
2021-12-01 11:05:29 +00:00
pack.ll
…
parity.ll
…
peephole-bitcast.ll
…
peephole-callee-save-regalloc.mir
…
peephole-phi.mir
…
pei-swiftself.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
phi.ll
…
pic.ll
…
pie.ll
…
plt-relative-reloc.ll
…
popcnt.ll
…
postrasched.ll
…
pow.75.ll
…
pow.ll
…
pr3502.ll
…
pr13249.ll
…
pr18364-movw.ll
…
pr25317.ll
…
pr25838.ll
…
pr26669.ll
…
pr32545.ll
…
pr32578.ll
…
pr34045-2.ll
…
pr34045.ll
…
pr35103.ll
…
pr36577.ll
…
pr39060.ll
…
pr39571.ll
…
pr42062.ll
…
pr42638-VMOVRRDCombine.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pr47454.ll
…
PR15053.ll
…
PR32721_ifcvt_triangle_unanalyzable.mir
…
PR35379.ll
…
preferred-align.ll
…
prefetch.ll
…
prera-ldst-aliasing.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prera-ldst-insertpt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
print-memb-operand.ll
…
print-registers.ll
…
private.ll
…
proc-resource-sched.ll
…
qdadd.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
rbit.ll
…
readcyclecounter.ll
…
readonly-aliases.ll
…
readtp.ll
[ARM] Use hardware TLS register in Thumb2 mode when -mtp=cp15 is passed
2021-10-27 16:42:11 -07:00
reg_sequence.ll
…
regcoal-invalid-subrange-update.mir
…
register-scavenger-exceptions.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regpair_hint_phys.ll
…
relax-per-target-feature.ll
…
rem_crash.ll
…
ret0.ll
…
ret_arg1.ll
…
ret_arg2.ll
…
ret_arg3.ll
…
ret_arg4.ll
…
ret_arg5.ll
…
ret_f32_arg2.ll
…
ret_f32_arg5.ll
…
ret_f64_arg2.ll
…
ret_f64_arg_reg_split.ll
…
ret_f64_arg_split.ll
…
ret_f64_arg_stack.ll
…
ret_i64_arg2.ll
…
ret_i64_arg3.ll
…
ret_i64_arg_split.ll
…
ret_i128_arg2.ll
…
ret_sret_vector.ll
…
ret_void.ll
…
returned-ext.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
returned-trunc-tail-calls.ll
…
rev.ll
[ARM] Expand rev.ll test with more triples. NFC
2021-11-23 14:24:58 +00:00
ror.ll
…
rotate.ll
[DAG] MatchRotate - support rotate-by-constant of illegal types
2021-11-19 11:12:04 +00:00
sadd_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
sadd_sat.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
sat-to-bitop.ll
…
saxpy10-a9.ll
…
sbfx.ll
…
sdiv-pow2-arm-size.ll
…
sdiv-pow2-thumb-size.ll
…
section-name.ll
…
section.ll
…
segmented-stacks-dynamic.ll
…
segmented-stacks.ll
…
select_const.ll
[ARM] Prevent continuous folding of SUBC
2021-09-15 11:23:32 +01:00
select_xform.ll
…
select-constant-xor.ll
[DAG] Fix GT -> GE condition when creating SetCC
2021-09-08 12:41:51 +01:00
select-imm.ll
…
select-undef.ll
…
select.ll
…
setcc-logic.ll
…
setcc-type-mismatch.ll
…
setjmp_longjmp.ll
…
shift_minsize.ll
…
shift-combine.ll
[ARM] Regenerate shift-combine.ll test checks
2021-11-04 14:27:31 +00:00
shift-i64.ll
…
shifter_operand.ll
[ARM] Define ComplexPatternFuncMutatesDAG
2021-08-06 17:35:11 +01:00
shuffle.ll
…
signext-inreg.ll
[LiveIntervals] Fix repairOldRegInRange for simple def cases
2021-09-24 11:44:49 +01:00
sincos.ll
[TargetLowering] Android has sincos functions
2018-09-18 13:18:21 +00:00
single-issue-r52.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sjlj-prepare-critical-edge.ll
…
sjljeh-swifterror.ll
…
sjljehprepare-lower-empty-struct.ll
…
smml.ll
…
smul.ll
…
SoftFloatVectorExtract.ll
…
softfp-constant-comparison.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
softfp-fabs-fneg.ll
…
space-directive.ll
…
special-reg-acore.ll
…
special-reg-mcore.ll
…
special-reg-v8m-base.ll
…
special-reg-v8m-main.ll
…
special-reg.ll
…
speculation-hardening-sls.ll
[ARM] Reset speculation-hardening-sls.ll test checks.
2021-10-05 10:51:18 +01:00
spill-q.ll
…
splitkit.ll
…
srem-seteq-illegal-types.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
ssat-lower.ll
…
ssat-unroll-loops.ll
…
ssat-upper.ll
…
ssat-v4t.ll
…
ssat-with-shift.ll
…
ssat.ll
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
2021-11-29 19:01:59 -08:00
ssp-data-layout.ll
[ARM] implement LOAD_STACK_GUARD for remaining targets
2021-11-08 22:59:15 +01:00
ssub_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
ssub_sat.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
stack_guard_remat.ll
…
stack-alignment.ll
…
stack-frame.ll
…
stack-guard-reassign.ll
[ARM] implement LOAD_STACK_GUARD for remaining targets
2021-11-08 22:59:15 +01:00
stack-guard-tls.ll
[ARM] implement support for TLS register based stack protector
2021-11-09 18:19:47 +01:00
stack-protector-bmovpcb_call.ll
…
stack-size-section.ll
…
stackpointer.ll
…
static-addr-hoisting.ll
…
stc2.ll
…
stm.ll
…
store_half.ll
…
store-postinc.ll
…
store-preinc.ll
…
store-prepostinc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
str_post.ll
…
str_pre-2.ll
…
str_pre.ll
…
str_trunc.ll
…
struct_byval_arm_t1_t2.ll
…
struct_byval.ll
[ARM] implement LOAD_STACK_GUARD for remaining targets
2021-11-08 22:59:15 +01:00
struct-byval-frame-index.ll
…
sub-cmp-peephole.ll
…
sub-from-const-hoisting.ll
…
sub-of-not.ll
…
sub.ll
…
subreg-remat.ll
…
subtarget-align.ll
[MC] Use local MCSubtargetInfo in writeNops
2021-09-07 15:46:19 +01:00
subtarget-features-long-calls.ll
…
subtarget-no-movt.ll
…
swift-atomics.ll
…
swift-ios.ll
…
swift-return.ll
…
swift-vldm.ll
…
swifterror.ll
…
swiftself.ll
…
swifttailcc-call.ll
…
swifttailcc-fastisel.ll
…
switch-minsize.ll
…
sxt_rot.ll
[ARM] Regenerate sxt_rot.ll tests
2021-11-21 18:33:29 +00:00
t2-imm.ll
…
t2-shrink-ldrpost.ll
…
t2abs-killflags.ll
…
tail-call-builtin.ll
…
tail-call-float.ll
…
tail-call-results.ll
…
tail-call-scheduling.ll
[ARM] implement LOAD_STACK_GUARD for remaining targets
2021-11-08 22:59:15 +01:00
tail-call-weak.ll
…
tail-call.ll
…
tail-dup-bundle.mir
…
tail-dup-kill-flags.ll
…
tail-dup.ll
…
tail-merge-branch-weight.ll
…
tail-opts.ll
…
tailcall-mem-intrinsics.ll
…
tailcc-call.ll
ARM: don't return by popping PC if we have to adjust the stack afterwards.
2021-07-21 09:35:14 +01:00
tailcc-notail.ll
…
taildup-branch-weight.ll
…
test-sharedidx.ll
Recommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
2021-07-06 12:16:05 -07:00
this-return.ll
…
thread_pointer.ll
[ARM] Use hardware TLS register in Thumb2 mode when -mtp=cp15 is passed
2021-10-27 16:42:11 -07:00
thumb1_return_sequence.ll
…
thumb1-div.ll
…
thumb1-ldst-opt.ll
…
thumb1-varalloc.ll
…
thumb2-it-block.ll
…
thumb2-size-opt.ll
…
thumb2-size-reduction-internal-flags.ll
…
thumb_indirect_calls.ll
…
thumb-alignment.ll
…
thumb-big-stack.ll
…
thumb-litpool.ll
…
thumb-stub.ll
…
tls1.ll
…
tls2.ll
…
tls3.ll
…
tls-models.ll
…
trap-unreachable.ll
…
trap.ll
…
trunc_ldr.ll
…
truncstore-dag-combine.ll
…
tst_teq.ll
…
tst-peephole.mir
…
two-part-imm.ll
…
twoaddrinstr.ll
…
uadd_sat_plus.ll
[ARM] Add lowering of uadd_sat to uq{add|sub}8 and uq{add|sub}16
2021-07-11 15:58:11 +01:00
uadd_sat.ll
[ARM] Add lowering of uadd_sat to uq{add|sub}8 and uq{add|sub}16
2021-07-11 15:58:11 +01:00
uint64tof64.ll
…
umulo-32.ll
…
umulo-64-legalisation-lowering.ll
…
umulo-128-legalisation-lowering.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
unaligned_load_store_vector.ll
…
unaligned_load_store_vfp.ll
…
unaligned_load_store.ll
…
undef-sext.ll
…
undefined.ll
…
unfold-shifts.ll
…
unord.ll
…
unschedule-first-call.ll
…
unwind-fp.ll
…
unwind-init.ll
…
urem-opt-size.ll
…
urem-seteq-illegal-types.ll
[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)
2021-09-07 15:42:43 +08:00
usat-lower.ll
…
usat-upper.ll
…
usat-v4t.ll
…
usat-with-shift.ll
…
usat.ll
[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
2021-11-29 19:01:59 -08:00
useaa.ll
…
usub_sat_plus.ll
[ARM] Add lowering of uadd_sat to uq{add|sub}8 and uq{add|sub}16
2021-07-11 15:58:11 +01:00
usub_sat.ll
[ARM] Add lowering of uadd_sat to uq{add|sub}8 and uq{add|sub}16
2021-07-11 15:58:11 +01:00
uxt_rot.ll
…
uxtb.ll
…
v1-constant-fold.ll
…
v6-jumptable-clobber.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
v6m-smul-with-overflow.ll
…
v6m-umul-with-overflow.ll
…
v7k-abi-align.ll
…
v7k-libcalls.ll
…
v7k-sincos.ll
…
v8m-tail-call.ll
…
v8m.base-jumptable_alignment.ll
…
va_arg.ll
…
vaba.ll
…
vabd.ll
…
vabs.ll
…
vadd.ll
…
vararg_no_start.ll
…
varargs-spill-stack-align-nacl.ll
…
vargs_align.ll
…
vargs.ll
…
vbits.ll
…
vbsl-constant.ll
…
vbsl.ll
…
vceq.ll
…
vcge.ll
…
vcgt.ll
…
vcnt.ll
…
vcombine.ll
…
vcvt_combine.ll
…
vcvt-cost.ll
Port the cost model printer to New PM
2021-09-08 14:47:05 -07:00
vcvt-v8.ll
…
vcvt.ll
…
vdiv_combine.ll
…
vdup.ll
…
vecreduce-fadd-legalization-soft-float.ll
…
vecreduce-fadd-legalization-strict.ll
…
vecreduce-fmax-legalization-soft-float.ll
…
vecreduce-fmin-legalization-soft-float.ll
…
vecreduce-fmul-legalization-soft-float.ll
…
vecreduce-fmul-legalization-strict.ll
…
vector-DAGCombine.ll
…
vector-extend-narrow.ll
…
vector-extract.ll
[ARM] Fix a bug in finding a pair of extracts to create VMOVRRD
2021-10-06 10:03:32 -07:00
vector-load.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
vector-promotion.ll
[ARM] Remove PromotedBitwiseVT for NEON types
2021-07-19 16:36:33 +01:00
vector-spilling.ll
…
vector-store.ll
…
vext.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
vfcmp.ll
…
vfloatintrinsics.ll
[ARM] Use correct name of floating point ceil intrinsic in test.
2021-10-20 17:30:26 -07:00
vfp-libcalls.ll
…
vfp-reg-stride.ll
…
vfp-regs-dwarf.ll
…
vfp.ll
…
vget_lane.ll
…
vhadd.ll
…
vhsub.ll
…
vicmp-64.ll
…
vicmp.ll
…
virtregrewriter-subregliveness.mir
…
vld1.ll
…
vld2.ll
…
vld3.ll
…
vld4.ll
…
vld-vst-upgrade.ll
[ARM] Support neon.vld auto-upgrade with opaque pointers
2021-09-11 16:34:32 +02:00
vlddup.ll
…
vldlane.ll
…
vldm-liveness.ll
…
vldm-liveness.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vldm-sched-a9.ll
…
vldmia-sched.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vlldm-vlstm-uops.mir
…
vminmax.ll
…
vminmaxnm-safe.ll
…
vminmaxnm.ll
…
vmla.ll
…
vmls.ll
…
vmov.ll
[ARM] Remove PromotedBitwiseVT for NEON types
2021-07-19 16:36:33 +01:00
vmul.ll
[Local] Do not introduce a new llvm.trap before unreachable
2021-07-26 23:33:36 -05:00
vneg.ll
…
vpadal.ll
…
vpadd.ll
…
vpminmax.ll
…
vqadd.ll
…
vqdmul.ll
…
vqshl.ll
…
vqshrn.ll
…
vqsub.ll
…
vrec.ll
…
vrev.ll
…
vrint.ll
…
vsel-fp16.ll
…
vsel.ll
…
vselect_imax.ll
[ARM] Simplify address calculation for NEON load/store
2021-10-14 15:23:10 +03:00
vshift.ll
…
vshiftins.ll
…
vshl.ll
…
vshll.ll
…
vshrn.ll
…
vsra.ll
…
vst1.ll
…
vst2.ll
…
vst3.ll
…
vst4.ll
…
vstlane.ll
…
vsub.ll
…
vtbl.ll
…
vtrn.ll
…
vuzp.ll
…
vzip.ll
…
warn-stack.ll
…
weak2.ll
…
weak.ll
…
wide-compares.ll
…
widen-vmovs.ll
…
win32-ssp.ll
[ARM] implement LOAD_STACK_GUARD for remaining targets
2021-11-08 22:59:15 +01:00
wrong-t2stmia-size-opt.ll
…
xray-armv6-attribute-instrumentation.ll
…
xray-armv7-attribute-instrumentation.ll
…
xray-tail-call-sled.ll
…
zero-cycle-zero.ll
…
zext-logic-shift-load.ll
…
zextload_demandedbits.ll
…