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llvm-project/llvm/test/MC/Disassembler/PowerPC
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Stefan Pintilie 2e55bc9f3c [PowerPC] Set the special DSCR with a compiler option.
Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be set by default.

Original patch by: Muhammad Usman

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D117013
2022-03-31 14:06:30 -05:00
..
dcbt.txt
…
lit.local.cfg
…
p10insts.txt
…
ppc32-extpid-e500.txt
…
ppc64-encoding-4xx.txt
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ppc64-encoding-6xx.txt
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ppc64-encoding-bookII.txt
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ppc64-encoding-bookIII.txt
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ppc64-encoding-e500.txt
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ppc64-encoding-ext.txt
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ppc64-encoding-fp.txt
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ppc64-encoding-ISA31-invalid.txt
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ppc64-encoding-ISA31.txt
[PowerPC] Add the Power10 LXVKQ instrution.
2022-02-23 08:48:59 -06:00
ppc64-encoding-p8htm.txt
…
ppc64-encoding-p8vector.txt
…
ppc64-encoding-p9vector.txt
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0
2017-05-11 22:17:35 +00:00
ppc64-encoding-vmx.txt
…
ppc64-encoding.txt
[PowerPC] Set the special DSCR with a compiler option.
2022-03-31 14:06:30 -05:00
ppc64-operands.txt
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ppc64le-encoding.txt
…
vsx.txt
…
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