07f7c00208
This patch adds the support required for using the __riscv_save and __riscv_restore libcalls to implement a size-optimization for prologue and epilogue code, whereby the spill and restore code of callee-saved registers is implemented by common functions to reduce code duplication. Logic is also included to ensure that if both this optimization and shrink wrapping are enabled then the prologue and epilogue code can be safely inserted into the basic blocks chosen by shrink wrapping. Differential Revision: https://reviews.llvm.org/D62686
144 lines
5.5 KiB
TableGen
144 lines
5.5 KiB
TableGen
//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<"FeatureStdExtM",
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"'M' (Integer Multiplication and Division)">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<"FeatureStdExtA",
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"'A' (Atomic Instructions)">;
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def FeatureStdExtF
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: SubtargetFeature<"f", "HasStdExtF", "true",
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"'F' (Single-Precision Floating-Point)">;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<"FeatureStdExtF",
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"'F' (Single-Precision Floating-Point)">;
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def FeatureStdExtD
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: SubtargetFeature<"d", "HasStdExtD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
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AssemblerPredicate<"FeatureStdExtD",
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"'D' (Double-Precision Floating-Point)">;
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def FeatureStdExtC
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: SubtargetFeature<"c", "HasStdExtC", "true",
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"'C' (Compressed Instructions)">;
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<"FeatureStdExtC",
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"'C' (Compressed Instructions)">;
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def FeatureRVCHints
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: SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
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"Enable RVC Hint Instructions.">;
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def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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AssemblerPredicate<"FeatureRVCHints",
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"RVC Hint Instructions">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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def IsRV64 : Predicate<"Subtarget->is64Bit()">,
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AssemblerPredicate<"Feature64Bit",
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"RV64I Base Instruction Set">;
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def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
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AssemblerPredicate<"!Feature64Bit",
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"RV32I Base Instruction Set">;
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def RV64 : HwMode<"+64bit">;
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def RV32 : HwMode<"-64bit">;
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def FeatureRV32E
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: SubtargetFeature<"e", "IsRV32E", "true",
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"Implements RV32E (provides 16 rather than 32 GPRs)">;
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def IsRV32E : Predicate<"Subtarget->isRV32E()">,
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AssemblerPredicate<"FeatureRV32E">;
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def FeatureRelax
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: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
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"Enable Linker relaxation.">;
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foreach i = {1-31} in
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def FeatureReserveX#i :
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SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
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"true", "Reserve X"#i>;
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def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
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"true", "Enable save/restore.">;
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//===----------------------------------------------------------------------===//
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// Named operands for CSR instructions.
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//===----------------------------------------------------------------------===//
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include "RISCVSystemOperands.td"
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//===----------------------------------------------------------------------===//
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// Registers, calling conventions, instruction descriptions.
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//===----------------------------------------------------------------------===//
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include "RISCVSchedule.td"
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include "RISCVRegisterInfo.td"
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include "RISCVCallingConv.td"
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include "RISCVInstrInfo.td"
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include "RISCVRegisterBanks.td"
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include "RISCVSchedRocket32.td"
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include "RISCVSchedRocket64.td"
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
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FeatureRVCHints]>;
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def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
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def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
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FeatureRVCHints]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//
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def RISCVInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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}
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def RISCVAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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let AllowDuplicateRegisterNames = 1;
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}
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def RISCVAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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let AssemblyParsers = [RISCVAsmParser];
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let AssemblyWriters = [RISCVAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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