96 lines
3.4 KiB
LLVM
96 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_and_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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