shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Kazu Hirata 83cb8b7bef
[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150841) 
LLVM Coding Standards discourages {std,llvm}::for_each unless we
already have a callable.
2025-07-27 10:43:52 -07:00
..
AsmParser
[RISCV] Handle 'c.addi x0, $imm' alias for c.nop using PseudoC_ADDI_NOP. (#150719)
2025-07-25 20:55:52 -07:00
Disassembler
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
GISel
[RISCV] Fix a warning
2025-05-30 10:27:57 -07:00
MCA
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
MCTargetDesc
MC: Generate relocation for a branch crossing linker-relaxable FT_Align fragment
2025-07-26 21:19:48 -07:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
CMakeLists.txt
[RISCV][NFC] Split InterleavedAccess related TLI hooks into a separate file (#148040)
2025-07-11 11:04:41 -07:00
RISCV.h
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVCallingConv.cpp
[RISCV] Guard the alternative static chain register use on ILP32E/LP64E (#142715)
2025-06-12 02:24:10 +08:00
RISCVCallingConv.h
…
RISCVCallingConv.td
[RISCV][llvm] Handle vector callee saved register correctly (#149467)
2025-07-21 17:49:34 -07:00
RISCVCodeGenPrepare.cpp
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)
2025-05-29 10:21:38 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. (#145836)
2025-06-27 10:54:41 +08:00
RISCVFeatures.td
[RISCV] Add missing Zvl dependencies for XSfvqmaccdod/XSfvqmaccqoq/XSfvfwmaccqqq. (#150346)
2025-07-23 22:06:46 -07:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150841)
2025-07-27 10:43:52 -07:00
RISCVFrameLowering.h
[RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531)
2025-07-15 08:09:18 -07:00
RISCVGatherScatterLowering.cpp
…
RISCVGISel.td
[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)
2025-04-28 09:26:34 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)
2025-05-28 14:56:44 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
2025-07-09 16:25:22 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrFormats.td
[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m (#149698)
2025-07-21 14:51:41 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfo.cpp
[RISCV] Remove now unused immzero operand type. NFC
2025-07-25 21:16:07 -07:00
RISCVInstrInfo.h
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfo.td
[RISCV][FPEnv] Lowering of fpmode intrinsics (#148569)
2025-07-16 16:02:15 +07:00
RISCVInstrInfoA.td
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
RISCVInstrInfoC.td
[RISCV] Accept c.slli/c.srli/c.srli with a 0 immediate as hints. (#150689)
2025-07-26 00:05:33 -07:00
RISCVInstrInfoD.td
[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
2025-05-15 08:35:43 -07:00
RISCVInstrInfoF.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoM.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoP.td
[RISCV] Rename RVPUnaryWUF to RVPUnary_ri for consistency. NFC
2025-07-23 13:11:44 -07:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV] Fix VLOptimizer assert, relax ElementsDependOn on viota/vms{b,i,o}f.m (#149698)
2025-07-21 14:51:41 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove empty pattern argument from RISCVVPseudo instantiations. NFC (#150554)
2025-07-24 19:40:35 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Select disjoint_or+not as xnor. (#147636)
2025-07-08 21:50:23 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Select disjoint_or+not as xnor. (#147636)
2025-07-08 21:50:23 -07:00
RISCVInstrInfoXAndes.td
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
2025-07-25 11:29:17 +08:00
RISCVInstrInfoXCV.td
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVInstrInfoXMips.td
[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)
2025-07-03 10:59:10 +02:00
RISCVInstrInfoXqccmp.td
[RISCV] Prefer RegList over Rlist in assembler. NFC
2025-04-04 09:37:52 -07:00
RISCVInstrInfoXqci.td
[RISCV] Swap source register operands in QC_SHLADD ISEL patterns (#149697)
2025-07-21 12:03:55 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
2025-07-23 16:29:12 +08:00
RISCVInstrInfoXSf.td
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
2025-07-23 16:29:12 +08:00
RISCVInstrInfoXSfmm.td
[RISCV] Add MC layer support for XSfmm*. (#133031)
2025-05-21 08:26:35 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Rename XTHeadVdot instructions to match their mnemonic. NFC (#146953)
2025-07-03 13:43:34 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
…
RISCVInstrInfoZalasr.td
[TableGen][SelectionDAG][GISel][RISCV] Support IsNonExtLoad for IsAtomic PatFrags. (#137401)
2025-04-25 15:45:43 -07:00
RISCVInstrInfoZb.td
[RISCV] Add Commutable flag to XNOR. (#147654)
2025-07-09 07:54:07 -07:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
2025-04-08 17:53:39 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV] Fix schedule info for FMVP_D_X. (#140766)
2025-05-22 08:39:57 -07:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[NFC][RISCV] Remove extra space in RISCVInstrInfoZfh.td
2025-05-13 13:53:38 +08:00
RISCVInstrInfoZicbo.td
[RISCV] Change the InstFormat for Zicbop prefetch instructions to InstFormatOther. (#148934)
2025-07-15 14:49:54 -07:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZk.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Make RISCVVPseudo extend Pseudo. NFC (#149785)
2025-07-23 16:29:12 +08:00
RISCVInstrInfoZvqdotq.td
[RISCV] Fix schedule info for Zqvdotq (#142717)
2025-06-05 12:22:43 +08:00
RISCVInstrPredicates.td
[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)
2025-07-03 12:47:53 +08:00
RISCVInterleavedAccess.cpp
[RISCV][IA] Rework VL for strided LD/ST optimization [nfc] (#150525)
2025-07-24 21:12:28 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)
2025-07-22 21:10:52 -07:00
RISCVISelDAGToDAG.h
[RISCV] Add a non-template version of SelectAddrRegZextRegScale and move code there. NFC
2025-07-19 17:53:39 -07:00
RISCVISelLowering.cpp
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
2025-07-25 11:29:17 +08:00
RISCVISelLowering.h
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
2025-07-25 11:29:17 +08:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
2025-06-23 10:49:47 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Avoid vl toggles when lowering vector_splice/experimental_vp_splice and add +vl-dependent-latency tuning feature (#146746)
2025-07-09 11:09:13 +08:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
2025-06-23 10:49:47 -07:00
RISCVRegisterInfo.h
[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
2025-03-20 15:20:04 -04:00
RISCVRegisterInfo.td
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (#150710)
2025-07-25 20:55:15 -07:00
RISCVSchedAndes45.td
[RISCV] Add short forward branch scheduling for Andes45 (#147890)
2025-07-14 09:26:19 +08:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISC-V] Update SpacemiT-X60 Vector Integer latencies (#149207)
2025-07-24 15:53:39 -03:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVScheduleV.td
[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)
2025-05-12 12:05:50 +08:00
RISCVScheduleXSf.td
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
2025-07-09 09:38:44 -07:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] Add TUPLE_INSERT and TUPLE_EXTRACT to verifyTargetNode. (#150148)
2025-07-22 18:28:11 -07:00
RISCVSelectionDAGInfo.h
[RISCV] Add RISCVISD::VQDOT*_VL to RISCVSelectionDAGInfo::verifyTargetNode. (#142202)
2025-05-30 22:33:29 -07:00
RISCVSubtarget.cpp
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSubtarget.h
[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)
2025-07-22 15:55:12 +08:00
RISCVSystemOperands.td
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967)
2025-05-22 08:46:48 -07:00
RISCVTargetMachine.cpp
[RISCV] Remove -riscv-enable-vl-optimizer flag (#149349)
2025-07-25 12:34:09 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
Revert "[RISCV][TTI] Enable masked interleave access for scalable vector (#149981)"
2025-07-25 16:14:10 +01:00
RISCVTargetTransformInfo.h
Revert "[RISCV][TTI] Enable masked interleave access for scalable vector (#149981)"
2025-07-25 16:14:10 +01:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
[RISCV] Don't lose elements from False in vmerge -> vmv peephole (#149720)
2025-07-22 15:21:42 +08:00
RISCVVLOptimizer.cpp
[RISCV] Simplify mask operand check in VLOptimizer. NFC (#150373)
2025-07-24 20:38:36 +08:00
RISCVVMV0Elimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVZacasABIFix.cpp
…