llvm-project

AsmParser

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

Disassembler

[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514 )

2025-09-23 06:03:30 +00:00

GISel

[RISCV] Support scalar llvm.fmodf intrinsic. (#161743 )

2025-10-03 08:05:24 -07:00

MCA

[MCA][RISCV]Enable latency instrument on RISCV (#160063 )

2025-09-23 09:50:34 -07:00

MCTargetDesc

[RISCV] Use SignExtend64<32> instead of ORing in 32 1s into upper bits in RISCVMatInt. NFC (#159864 )

2025-09-21 23:08:19 -07:00

TargetInfo

[RISCV] Add initial assembler/MC layer support for big-endian (#146534 )

2025-08-22 09:21:10 +02:00

CMakeLists.txt

Recommit "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156798 )"

2025-09-04 09:50:12 -07:00

RISCV.h

Register assembly printer passes (#138348 )

2025-05-06 18:01:17 -07:00

RISCV.td

[RISCV] Implement base scheduling model for andes 45 series processor. (#141008 )

2025-06-04 16:11:43 +08:00

RISCVAsmPrinter.cpp

[RISCV] Simplify interface of RISCVAsmPrinter::lowerToMCInst [nfc] (#156482 )

2025-09-02 14:56:26 -07:00

RISCVCallingConv.cpp

[CodeGen] Provide original IR type to CC lowering (NFC) (#152709 )

2025-08-11 08:57:53 +02:00

RISCVCallingConv.h

[CodeGen] Provide original IR type to CC lowering (NFC) (#152709 )

2025-08-11 08:57:53 +02:00

RISCVCallingConv.td

[RISCV] Support PreserveMost calling convention (#148214 )

2025-07-30 16:30:48 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Widen i1 AnyOf reductions (#134898 )

2025-04-28 10:07:51 +08:00

RISCVCombine.td

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RISCVConstantPoolValue.cpp

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RISCVConstantPoolValue.h

…

RISCVDeadRegisterDefinitions.cpp

CodeGen: Remove MachineFunction argument from getRegClass (#158188 )

2025-09-12 19:22:02 +09:00

RISCVExpandAtomicPseudoInsts.cpp

[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279 )

2025-04-03 11:28:45 -07:00

RISCVExpandPseudoInsts.cpp

[RISCV] Xqci with Short Forward Branches (#161407 )

2025-10-01 10:00:40 -07:00

RISCVFeatures.td

[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514 )

2025-09-23 06:03:30 +00:00

RISCVFoldMemOffset.cpp

[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762 )

2025-04-22 19:24:29 -07:00

RISCVFrameLowering.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVFrameLowering.h

[RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531 )

2025-07-15 08:09:18 -07:00

RISCVGatherScatterLowering.cpp

[RISCV] Use non-vp select in RISCVGatherScatterLowering. NFCish (#157071 )

2025-09-06 11:46:02 +08:00

RISCVGISel.td

[RISCV] Remove unusable pattern from RISCVGISel.td. NFC

2025-10-03 14:37:46 -07:00

RISCVIndirectBranchTracking.cpp

[RISCV][NFC] Fix typo in RISCVIndirectBranchTracking.cpp (#157221 )

2025-09-08 15:02:48 +08:00

RISCVInsertReadWriteCSR.cpp

…

RISCVInsertVSETVLI.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVInsertWriteVXRM.cpp

[RISCV][NFC] Convert some predicates to TIIPredicate (#129658 )

2025-04-30 16:59:05 +08:00

RISCVInstrFormats.td

[RISCV][MC] Add MC support of Zibi experimental extension (#127463 )

2025-09-12 15:38:41 +08:00

RISCVInstrFormatsC.td

[RISCV] Remove post-decoding instruction adjustments (#156360 )

2025-09-04 16:02:34 +00:00

RISCVInstrFormatsV.td

[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104 )

2025-02-27 13:14:22 -08:00

RISCVInstrGISel.td

[RISCV] TableGen-erate RISC-V SDNodes (#138381 )

2025-05-09 12:36:59 -07:00

RISCVInstrInfo.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVInstrInfo.h

[RISCV][NFC] Rename getOppositeBranchCondition (#160972 )

2025-09-29 19:15:41 +01:00

RISCVInstrInfo.td

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

RISCVInstrInfoA.td

[RISCV][GISel] Share an atomic load isel pattern GISel RV64 and SDAG RV32. NFC (#161721 )

2025-10-02 12:50:09 -07:00

RISCVInstrInfoC.td

[TableGen][DecoderEmitter][RISCV] Always handle bits<0> (#159951 )

2025-09-22 20:50:17 +03:00

RISCVInstrInfoD.td

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

RISCVInstrInfoF.td

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

RISCVInstrInfoM.td

[RISCV][NFC] Cleanup Negative Predicate Names (#155017 )

2025-08-22 14:46:41 -07:00

RISCVInstrInfoP.td

[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247 )

2025-09-19 13:08:23 +10:00

RISCVInstrInfoQ.td

[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495 )

2025-05-15 10:58:13 +08:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

RISCVInstrInfoV.td

[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (#159619 )

2025-09-19 23:57:59 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Improve formatting in RISCVInstrInfoVPseudos.td. NFC (#161470 )

2025-10-02 12:29:24 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoXAndes.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoXCV.td

[RISCV][NFC] Rename simm12 to simm12_lo (#160380 )

2025-09-23 21:09:26 +00:00

RISCVInstrInfoXMips.td

RISC-V: builtins support for MIPS RV64 P8700 execution control .

2025-09-19 15:10:28 +05:30

RISCVInstrInfoXqccmp.td

[RISCV] Prefer RegList over Rlist in assembler. NFC

2025-04-04 09:37:52 -07:00

RISCVInstrInfoXqci.td

[RISCV] Xqci with Short Forward Branches (#161407 )

2025-10-01 10:00:40 -07:00

RISCVInstrInfoXRivos.td

[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704 )

2025-08-15 01:19:03 +00:00

RISCVInstrInfoXSf.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoXSfmm.td

[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704 )

2025-08-15 01:19:03 +00:00

RISCVInstrInfoXSpacemiT.td

[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.

2025-08-21 13:12:46 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483 )

2025-09-15 00:57:31 +03:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoXwch.td

[RISCV] Remove post-decoding instruction adjustments (#156360 )

2025-09-04 16:02:34 +00:00

RISCVInstrInfoZa.td

[RISCV][NFC] Cleanup Negative Predicate Names (#155017 )

2025-08-22 14:46:41 -07:00

RISCVInstrInfoZalasr.td

[RISCV] Reverse the operands in ins for Zalasr store instructions. NFC (#161882 )

2025-10-03 13:09:10 -07:00

RISCVInstrInfoZb.td

[RISCV] Use bseti 31 for (or X, -2147483648) when upper 32 bits aren't used. (#159678 )

2025-09-18 17:33:08 -07:00

RISCVInstrInfoZc.td

[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541 )

2025-07-24 18:03:30 -07:00

RISCVInstrInfoZclsd.td

[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946 )

2025-04-08 17:53:39 -07:00

RISCVInstrInfoZcmop.td

[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289 )

2025-08-25 14:06:28 -07:00

RISCVInstrInfoZfa.td

[RISCV] Fix schedule info for FMVP_D_X. (#140766 )

2025-05-22 08:39:57 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Add isel for bitcasting between bfloat and half types (#158828 )

2025-09-17 12:10:47 -07:00

RISCVInstrInfoZfh.td

[RISCV] Add Predicates to fcanonicalize patterns. NFC (#158709 )

2025-09-15 12:51:01 -07:00

RISCVInstrInfoZibi.td

[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858 )

2025-09-18 11:03:48 +08:00

RISCVInstrInfoZicbo.td

[RISCV][NFC] Cleanup Negative Predicate Names (#155017 )

2025-08-22 14:46:41 -07:00

RISCVInstrInfoZicfiss.td

[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483 )

2025-09-15 00:57:31 +03:00

RISCVInstrInfoZicond.td

[RISCV] TableGen-erate RISC-V SDNodes (#138381 )

2025-05-09 12:36:59 -07:00

RISCVInstrInfoZilsd.td

[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808 )

2025-05-14 09:54:07 -07:00

RISCVInstrInfoZimop.td

[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289 )

2025-08-25 14:06:28 -07:00

RISCVInstrInfoZk.td

[RISCV] TableGen-erate RISC-V SDNodes (#138381 )

2025-05-09 12:36:59 -07:00

RISCVInstrInfoZvfbf.td

[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469 )

2025-09-30 19:53:21 -07:00

RISCVInstrInfoZvfofp8min.td

[RISCV] Implement MC support for Zvfofp8min extension (#157014 )

2025-09-19 07:49:31 +00:00

RISCVInstrInfoZvk.td

[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835 )

2025-08-02 21:53:58 -07:00

RISCVInstrInfoZvqdotq.td

[RISCV] Support ZVqdot Codegen and C intrinsics (#154915 )

2025-09-05 11:38:58 +08:00

RISCVInstrPredicates.td

[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858 )

2025-09-18 11:03:48 +08:00

RISCVInterleavedAccess.cpp

[IA][RISCV] Recognize interleaving stores that could lower to strided segmented stores (#154647 )

2025-08-26 13:22:42 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Refactor DAG-to-DAG Selection: Port lowering code for qc.insb/qc.insbi to RISCVISelLowering.cpp (#157618 )

2025-09-24 08:32:59 +05:30

RISCVISelDAGToDAG.h

[RISCV] Refactor DAG-to-DAG Selection: Port lowering code for qc.insb/qc.insbi to RISCVISelLowering.cpp (#157618 )

2025-09-24 08:32:59 +05:30

RISCVISelLowering.cpp

[RISCV] Support scalar llvm.fmodf intrinsic. (#161743 )

2025-10-03 08:05:24 -07:00

RISCVISelLowering.h

Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470 )"

2025-09-26 17:24:56 -07:00

RISCVLandingPadSetup.cpp

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RISCVLateBranchOpt.cpp

[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762 )

2025-06-25 23:09:24 -07:00

RISCVLoadStoreOptimizer.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101 )

2025-05-23 08:30:29 -07:00

RISCVMachineFunctionInfo.cpp

[RISCV] SiFive CLIC Support (#132481 )

2025-04-25 17:12:27 -07:00

RISCVMachineFunctionInfo.h

[RISCV] SiFive CLIC Support (#132481 )

2025-04-25 17:12:27 -07:00

RISCVMacroFusion.td

[RISCV] add more generic macrofusions (#151140 )

2025-08-06 14:46:34 -04:00

RISCVMakeCompressible.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVMergeBaseOffset.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101 )

2025-05-23 08:30:29 -07:00

RISCVMoveMerger.cpp

[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467 )

2025-08-20 09:07:58 -07:00

RISCVOptWInstrs.cpp

[RISCV] Add TH_EXT(U) to hasAllNBitUsers in RISCVOptWInstrs. (#157544 )

2025-09-09 08:47:39 -07:00

RISCVPfmCounters.td

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RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Remove Zicntr from sifive-p450/p470/p670. (#161444 )

2025-09-30 19:14:30 -07:00

RISCVProfiles.td

[RISCV][NFC] Add Zicsr to profiles explicitly (#136134 )

2025-04-18 10:59:32 +08:00

RISCVPushPopOptimizer.cpp

[RISCV] Simplify how we find combinable cm.pop+ret. (#130204 )

2025-03-06 21:55:47 -08:00

RISCVRedundantCopyElimination.cpp

[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762 )

2025-06-25 23:09:24 -07:00

RISCVRegisterInfo.cpp

[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693 )

2025-08-27 15:59:08 -07:00

RISCVRegisterInfo.h

CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185 )

2025-09-12 09:18:50 +00:00

RISCVRegisterInfo.td

[RISCV] Fix GPRPairNoX0 Disassembly (#158001 )

2025-09-11 08:51:37 -07:00

RISCVSchedAndes45.td

[RISCV] Fix typo in comment Interger->Integer. NFC

2025-08-13 11:19:49 -07:00

RISCVSchedGenericOOO.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedMIPSP8700.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedRocket.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSiFive7.td

[RISCV] Update SiFive7's scheduling models with their optimizations on permutation instructions (#160763 )

2025-09-26 11:08:51 -07:00

RISCVSchedSiFiveP400.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSiFiveP500.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSiFiveP600.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSiFiveP800.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSpacemitX60.td

[RISCV] Update SpacemiT-X60 vector fixed-point arithmetic latencies (#150517 )

2025-08-08 11:57:35 -03:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSyntacoreSCR7.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedTTAscalonD8.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSchedule.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVScheduleV.td

[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938 )

2025-05-12 12:05:50 +08:00

RISCVScheduleXSf.td

[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626 )

2025-07-09 09:38:44 -07:00

RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666 )

2025-07-10 14:15:22 +08:00

RISCVSelectionDAGInfo.cpp

[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555 )

2025-08-04 12:51:14 +05:30

RISCVSelectionDAGInfo.h

[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555 )

2025-08-04 12:51:14 +05:30

RISCVSubtarget.cpp

[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297 )

2025-07-22 15:55:12 +08:00

RISCVSubtarget.h

[RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC (#158775 )

2025-09-16 10:25:19 -07:00

RISCVSystemOperands.td

[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967 )

2025-05-22 08:46:48 -07:00

RISCVTargetMachine.cpp

[RISCV] Enabled debug entry support by default (#157703 )

2025-09-12 11:49:33 +03:00

RISCVTargetMachine.h

[CodeGen] Move MISched target hooks into TargetMachine (#125700 )

2025-02-05 11:41:37 +05:30

RISCVTargetObjectFile.cpp

RISCV: Replace RISCVMCExpr with MCSpecifierExpr

2025-06-15 16:51:09 -07:00

RISCVTargetObjectFile.h

RISCV: Replace RISCVMCExpr with MCSpecifierExpr

2025-06-15 16:51:09 -07:00

RISCVTargetTransformInfo.cpp

[RISCV] Allow non-canonicalized splats in isProfitableToSinkOperands (#161586 )

2025-10-01 14:00:28 -07:00

RISCVTargetTransformInfo.h

Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470 )"

2025-09-26 17:24:56 -07:00

RISCVVectorMaskDAGMutation.cpp

Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855 )" (#148566 )

2025-07-18 10:56:07 +08:00

RISCVVectorPeephole.cpp

[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781 )

2025-10-03 08:53:58 -07:00

RISCVVLOptimizer.cpp

[RISCV] Ignore debug instructions in RISCVVLOptimizer (#159616 )

2025-09-19 12:22:44 +08:00

RISCVVMV0Elimination.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101 )

2025-05-23 08:30:29 -07:00

RISCVZacasABIFix.cpp

…