Philip Reames f14224d92b

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563) ...

The prior naming scheme is incredibly hard to make sense out of. I
suspect the usage was actually backwards from intent - though that
didn't matter for any in tree schedule model.

2024-03-11 07:52:28 -07:00

..

AsmParser

[RISCV] Fix typo in call to clearFeatureBits.

2024-02-06 12:19:27 -08:00

Disassembler

[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variable warning. (#80651)

2024-02-06 14:41:47 +08:00

GISel

[GlobalIsel] Lower integer constants to constant pool in LegalizerHelper. (#81957)

2024-02-16 18:51:44 -05:00

MCA

[RISCV] Add TargetParser to MCA (#84109)

2024-03-06 11:49:28 +08:00

MCTargetDesc

[RISCV] Move RISCVVType namespace to TargetParser (#83222)

2024-03-06 10:56:19 +08:00

TargetInfo

…

CMakeLists.txt

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770)

2024-02-26 12:12:31 +00:00

RISCV.h

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770)

2024-02-26 12:12:31 +00:00

RISCV.td

[RISCV] Add sched model for XiangShan-NanHu (#70232)

2024-02-12 15:00:54 +08:00

RISCVAsmPrinter.cpp

[RISCV] Use hasStdExtCOrZca instead of FeatureStdExtC to determine NOP size in RISCVAsmPrinter.cpp.

2024-02-06 12:39:04 -08:00

RISCVCallingConv.td

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

2024-01-16 20:44:30 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.

2024-01-19 14:44:47 -08:00

RISCVCombine.td

[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)

2023-09-22 10:13:56 -07:00

RISCVDeadRegisterDefinitions.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Support TLSDESC in the RISC-V backend (#66915)

2024-01-23 16:16:07 -08:00

RISCVFeatures.td

[RISCV] Remove note of Sscofpmf and add a newline after FeatureStdExtSscofpmf (#83958)

2024-03-05 14:26:54 +08:00

RISCVFoldMasks.cpp

[RISCV] Mark RISCVFoldMasks methods as const. NFC

2024-02-13 13:02:15 +08:00

RISCVFrameLowering.cpp

[RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc]

2024-02-20 17:27:47 -08:00

RISCVFrameLowering.h

[RISCV] Register fixed stack slots for callee saved registers for -msave-restore/Zcmp (#81392)

2024-02-13 14:59:28 -08:00

RISCVGatherScatterLowering.cpp

[NFC][RemoveDIs] Always use iterators for inserting PHIs

2024-03-05 17:00:12 +00:00

RISCVGISel.td

[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)

2023-12-04 13:00:34 -08:00

RISCVInsertReadWriteCSR.cpp

[RISCV] Implement foward inserting save/restore FRM instructions. (#77744)

2024-01-25 14:41:52 +08:00

RISCVInsertVSETVLI.cpp

[RISCV] Add statistic support for VSETVL insertion pass (#78543)

2024-01-19 08:22:25 +08:00

RISCVInsertWriteVXRM.cpp

[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578)

2024-01-02 09:50:06 -08:00

RISCVInstrFormats.td

[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)

2023-12-27 11:19:38 +08:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)

2023-11-22 16:43:20 -08:00

RISCVInstrInfo.cpp

[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)

2024-03-06 17:40:13 +00:00

RISCVInstrInfo.h

[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)

2024-03-06 17:40:13 +00:00

RISCVInstrInfo.td

[RISCV] Use TImmLeaf for csr_sysreg (#82463)

2024-02-21 15:04:29 +08:00

RISCVInstrInfoA.td

[RISCV][MC] Add experimental support of Zaamo and Zalrsc

2024-01-25 17:03:25 +08:00

RISCVInstrInfoC.td

[RISCV] Fix scheduling info for compressed LD/ST of FP types. (#82339)

2024-02-21 08:47:39 +01:00

RISCVInstrInfoD.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoF.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoM.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945)

2024-02-07 16:03:30 +08:00

RISCVInstrInfoV.td

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563)

2024-03-11 07:52:28 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563)

2024-03-11 07:52:28 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Select pattern (shl (sext_vl/zext_vl), 1) to VWADD/VWADDU. (#82225)

2024-02-20 09:23:31 +08:00

RISCVInstrInfoVVLPatterns.td

[RISCV][ISel] Remove redundant vmerge for the vwadd. (#78403)

2024-01-27 20:03:32 +09:00

RISCVInstrInfoXCV.td

[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)

2023-12-17 19:29:40 +08:00

RISCVInstrInfoXSf.td

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)

2024-01-26 11:15:53 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoZa.td

[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192)

2024-02-16 15:35:09 +08:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZc.td

[RISCV] Add scheduling info for Zcmp (#82719)

2024-02-23 15:44:57 -08:00

RISCVInstrInfoZcmop.td

[RISCV] Add MC layer support for Zicfiss. (#66043)

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZfa.td

[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)

2023-10-19 14:55:33 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)

2023-11-01 09:36:41 -07:00

RISCVInstrInfoZfh.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZicbo.td

[RISCV] Match prefetch address with offset (#66072)

2023-10-20 14:22:48 +08:00

RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043)

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811)

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV][ISel] Add ISel support for experimental Zimop extension (#77089)

2024-01-29 15:24:00 -08:00

RISCVInstrInfoZk.td

[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)

2023-10-08 14:13:08 +08:00

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV][NFC] Remove unused methods of tuimm5 (#79680)

2024-01-29 09:54:34 +08:00

RISCVISelDAGToDAG.cpp

[RISCV] Fix insert_subvector with fixed vector type creating invalid node (#82975)

2024-02-26 19:33:44 +08:00

RISCVISelDAGToDAG.h

[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)

2024-01-26 11:15:53 +08:00

RISCVISelLowering.cpp

[RISCV] Move NodeExtensionHelper assert to getOrCreateExtendedOp. NFC

2024-03-11 18:00:29 +08:00

RISCVISelLowering.h

[RISCV] Move RISCVVType namespace to TargetParser (#83222)

2024-03-06 10:56:19 +08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)

2023-09-25 12:05:05 +08:00

RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (#81844)

2024-02-22 15:51:19 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Merge ADDI with X0 into base offset (#78940)

2024-01-23 09:57:05 +08:00

RISCVMoveMerger.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVOptWInstrs.cpp

[RISCV] Rework isSignExtendingOpW to store Register in the worklist.

2024-02-03 23:40:09 -08:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)

2023-11-09 15:15:23 +08:00

RISCVProcessors.td

[RISCV] Add sched model for XiangShan-NanHu (#70232)

2024-02-12 15:00:54 +08:00

RISCVPushPopOptimizer.cpp

[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)

2024-02-07 14:30:45 -08:00

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV] Add a command line option to disable cost per use for compressed registers. (#83320)

2024-02-28 15:06:20 -08:00

RISCVRegisterInfo.h

[RISCV][NFC] Add helpers for RVV register classes

2024-03-07 14:18:37 +08:00

RISCVRegisterInfo.td

[RISCV] Use the VR register allocation order for VM. (#83664)

2024-03-02 17:06:38 -08:00

RISCVSchedRocket.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVSchedSiFive7.td

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563)

2024-03-11 07:52:28 -07:00

RISCVSchedSiFiveP400.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVSchedule.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVScheduleV.td

[RISCV] Rename schedule classes for vmv.s.x, vmv.x.s, vfmv.s.f, and vfmv.f.s [nfc] (#84563)

2024-03-11 07:52:28 -07:00

RISCVScheduleZb.td

…

RISCVSchedXiangShanNanHu.td

[RISCV] Split div vs rem scheduling information [nfc] (#84385)

2024-03-07 14:03:58 -08:00

RISCVSubtarget.cpp

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVSubtarget.h

[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770)

2024-02-26 12:12:31 +00:00

RISCVSystemOperands.td

[RISCV] Recognize CSR name ssp for Zicfilp. (#81974)

2024-02-17 09:56:22 +08:00

RISCVTargetMachine.cpp

[RISCV][NFC] Add helpers for RVV register classes

2024-03-07 14:18:37 +08:00

RISCVTargetMachine.h

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

2023-09-14 14:10:14 -07:00

RISCVTargetObjectFile.cpp

[RISCV] Place mergeable small read only data into srodata section (#82214)

2024-03-11 13:57:06 +08:00

RISCVTargetObjectFile.h

[RISCV] Place mergeable small read only data into srodata section (#82214)

2024-03-11 13:57:06 +08:00

RISCVTargetTransformInfo.cpp

[RISCV] Hoist immediate addresses from loads/stores (#83644)

2024-03-05 22:41:56 -08:00

RISCVTargetTransformInfo.h

[TTI]Add support for strided loads/stores.

2024-02-01 16:07:38 -05:00