Yaxun Liu 30e4608cca CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space ...

SelectionDAGISel::LowerArguments assumes sret addr space is 0, which is
not true for amdgcn---amdgiz target.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D40255

llvm-svn: 319630

2017-12-03 03:31:45 +00:00

..

AArch64

[DAG][AArch64] Disable post-legalization store

2017-12-02 04:01:26 +00:00

AMDGPU

CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space

2017-12-03 03:31:45 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[DAG][ARM] Revert "Reenable post-legalize store merge"

2017-12-01 21:55:47 +00:00

AVR

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

Support generic lowering of vector bswap

2017-11-30 11:06:22 +00:00

Hexagon

[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mir

2017-11-30 21:23:19 +00:00

Inputs

…

Lanai

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

Mips

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

MIR

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

MSP430

…

Nios2

…

NVPTX

[NVPTX] Implement __nvvm_atom_add_gen_d builtin.

2017-11-07 22:10:54 +00:00

PowerPC

Follow-up to r319434 to turn the pass on by default

2017-12-01 12:02:59 +00:00

RISCV

[RISCV] Use register X0 (ZERO) for constant 0

2017-11-21 08:23:08 +00:00

SPARC

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

SystemZ

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb2

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

WebAssembly

[WebAssembly] Revert r319186 "Support bitcasted function addresses with varargs."

2017-11-30 18:16:49 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

Revert "[X86] Improvement in CodeGen instruction selection for LEAs."

2017-12-01 22:20:26 +00:00

XCore

[MC] Suppress .Lcfi labels when emitting textual assembly

2017-10-10 00:57:36 +00:00