08165c444e
There are many information that can be used for tuning, like alignments, cache line size, etc. But we can't make all of them `SubtargetFeature` because some of them are not with enumerable value, for example, `PrefetchDistance` used by `LoopDataPrefetch`. In this patch, a searchable table `RISCVTuneInfoTable` is added, in which each entry contains the CPU name and all tune information defined in `RISCVTuneInfo`. Each field of `RISCVTuneInfo` should have a default value and processor definitions can override the default value via `let` statements. We don't need to define a `RISCVTuneInfo` for each processor and it will use the default value (which is for `generic`) if no `RISCVTuneInfo` defined. For processors in the same series, a subclass can inherit from `RISCVTuneInfo` and override the fields. And we can also override the fields in processor definitions if there are some differences in the same processor series. When initilizing `RISCVSubtarget`, we will use `TuneCPU` as the key to serach the tune info table. So, the behavior here is if we don't specify the tune CPU, we will use specified `CPU`, which is expected I think. This patch almost undoes 61ab106, in which I added tune features of preferred function/loop alignments. More tune information can be added in the future.
22 lines
778 B
LLVM
22 lines
778 B
LLVM
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32C
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; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
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; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-I
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; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+c < %s -o %t
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; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-C
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; SEC: Name Type Address Off Size ES Flg Lk Inf Al
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; SEC-I: .text PROGBITS 00000000 [[#%x,]] [[#%x,]] 00 AX 0 0 4
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; SEC-C: .text PROGBITS 00000000 [[#%x,]] [[#%x,]] 00 AX 0 0 2
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define void @foo() {
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;RV32I: .p2align 2
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;RV32I: foo:
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;RV32C: .p2align 1
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;RV32C: foo:
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entry:
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ret void
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}
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