18782db4c9
(seteq (and X, 1<<XLEN-1), 0) -> (xori (srli X, XLEN-1), 1)
(seteq (and X, 1<<31), 0) -> (xori (srliw X, 31), 1) // RV64
(setlt X, 0) -> (srli X, XLEN-1) // SRLI is compressible
(setlt (sext X), 0) -> (srliw X, 31) // RV64
73 lines
2.2 KiB
LLVM
73 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
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declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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define i1 @sadd(i32 %a, i32 %b, ptr %c) nounwind {
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; RV32I-LABEL: sadd:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: add a3, a0, a1
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; RV32I-NEXT: slt a0, a3, a0
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; RV32I-NEXT: srli a1, a1, 31
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; RV32I-NEXT: xor a0, a1, a0
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; RV32I-NEXT: sw a3, 0(a2)
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; RV32I-NEXT: ret
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entry:
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%x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%calc = extractvalue {i32, i1} %x, 0
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%ovf = extractvalue {i32, i1} %x, 1
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store i32 %calc, ptr %c
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ret i1 %ovf
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}
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define i1 @ssub(i32 %a, i32 %b, ptr %c) nounwind {
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; RV32I-LABEL: ssub:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: sgtz a3, a1
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: slt a0, a1, a0
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; RV32I-NEXT: xor a0, a3, a0
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; RV32I-NEXT: sw a1, 0(a2)
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; RV32I-NEXT: ret
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entry:
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%x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
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%calc = extractvalue {i32, i1} %x, 0
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%ovf = extractvalue {i32, i1} %x, 1
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store i32 %calc, ptr %c
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ret i1 %ovf
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}
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define i1 @uadd(i32 %a, i32 %b, ptr %c) nounwind {
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; RV32I-LABEL: uadd:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: add a1, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sw a1, 0(a2)
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; RV32I-NEXT: ret
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entry:
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%x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%calc = extractvalue {i32, i1} %x, 0
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%ovf = extractvalue {i32, i1} %x, 1
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store i32 %calc, ptr %c
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ret i1 %ovf
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}
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define i1 @usub(i32 %a, i32 %b, ptr %c) nounwind {
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; RV32I-LABEL: usub:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sw a1, 0(a2)
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; RV32I-NEXT: ret
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entry:
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%x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%calc = extractvalue {i32, i1} %x, 0
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%ovf = extractvalue {i32, i1} %x, 1
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store i32 %calc, ptr %c
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ret i1 %ovf
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}
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