Michael Maitland 84efad0b47
[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)
This fixes
https://discourse.llvm.org/t/fixed-register-being-spill-and-restored-in-clang/83058.

We need to do it in `MachineRegisterInfo::getCalleeSavedRegs` instead of
`RISCVRegisterInfo::getCalleeSavedRegs` since the MF argument of
`TargetRegisterInfo:::getCalleeSavedRegs` is `const`, so we can't call
`MF->getRegInfo().disableCalleeSavedRegister` there.

So to put it in `MachineRegisterInfo::getCalleeSavedRegs`, we move
`isRegisterReservedByUser` into `TargetSubtargetInfo`.
2024-12-06 14:07:27 -05:00

36 lines
1018 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 < %s | FileCheck %s
define noundef signext i32 @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: li s8, 321
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
tail call void @llvm.write_register.i64(metadata !0, i64 321)
ret i32 0
}
declare void @llvm.write_register.i64(metadata, i64)
define noundef signext i32 @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: li s8, 321
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
tail call void asm sideeffect "", "~{x25}"() #3
tail call void @llvm.write_register.i64(metadata !0, i64 321)
ret i32 0
}
!llvm.named.register.x24 = !{!0}
!0 = !{!"x24"}