1bc1a79a65
This would allow some inline assembly code to work with either F or Zfinx. This appears to match gcc behavior.
141 lines
4.6 KiB
LLVM
141 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32FINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zdinx -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64FINX %s
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@gd = external global double
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define double @constraint_r_double(double %a) nounwind {
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; RV32FINX-LABEL: constraint_r_double:
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; RV32FINX: # %bb.0:
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; RV32FINX-NEXT: lui a2, %hi(gd)
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; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2)
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; RV32FINX-NEXT: lw a2, %lo(gd)(a2)
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; RV32FINX-NEXT: #APP
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; RV32FINX-NEXT: fadd.d a0, a0, a2
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; RV32FINX-NEXT: #NO_APP
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; RV32FINX-NEXT: ret
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;
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; RV64FINX-LABEL: constraint_r_double:
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; RV64FINX: # %bb.0:
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; RV64FINX-NEXT: lui a1, %hi(gd)
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; RV64FINX-NEXT: ld a1, %lo(gd)(a1)
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; RV64FINX-NEXT: #APP
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; RV64FINX-NEXT: fadd.d a0, a0, a1
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; RV64FINX-NEXT: #NO_APP
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; RV64FINX-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "=r,r,r"(double %a, double %1)
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ret double %2
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}
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define double @constraint_cr_double(double %a) nounwind {
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; RV32FINX-LABEL: constraint_cr_double:
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; RV32FINX: # %bb.0:
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; RV32FINX-NEXT: lui a2, %hi(gd)
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; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2)
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; RV32FINX-NEXT: lw a2, %lo(gd)(a2)
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; RV32FINX-NEXT: #APP
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; RV32FINX-NEXT: fadd.d a0, a0, a2
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; RV32FINX-NEXT: #NO_APP
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; RV32FINX-NEXT: ret
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;
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; RV64FINX-LABEL: constraint_cr_double:
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; RV64FINX: # %bb.0:
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; RV64FINX-NEXT: lui a1, %hi(gd)
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; RV64FINX-NEXT: ld a1, %lo(gd)(a1)
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; RV64FINX-NEXT: #APP
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; RV64FINX-NEXT: fadd.d a0, a0, a1
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; RV64FINX-NEXT: #NO_APP
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; RV64FINX-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "=^cr,^cr,^cr"(double %a, double %1)
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ret double %2
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}
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define double @constraint_double_abi_name(double %a) nounwind {
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; RV32FINX-LABEL: constraint_double_abi_name:
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; RV32FINX: # %bb.0:
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; RV32FINX-NEXT: addi sp, sp, -16
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; RV32FINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
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; RV32FINX-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
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; RV32FINX-NEXT: lui a2, %hi(gd)
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; RV32FINX-NEXT: lw s0, %lo(gd)(a2)
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; RV32FINX-NEXT: lw s1, %lo(gd+4)(a2)
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; RV32FINX-NEXT: #APP
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; RV32FINX-NEXT: fadd.d t1, a0, s0
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; RV32FINX-NEXT: #NO_APP
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; RV32FINX-NEXT: mv a0, t1
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; RV32FINX-NEXT: mv a1, t2
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; RV32FINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
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; RV32FINX-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
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; RV32FINX-NEXT: addi sp, sp, 16
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; RV32FINX-NEXT: ret
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;
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; RV64FINX-LABEL: constraint_double_abi_name:
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; RV64FINX: # %bb.0:
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; RV64FINX-NEXT: addi sp, sp, -16
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; RV64FINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
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; RV64FINX-NEXT: lui a1, %hi(gd)
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; RV64FINX-NEXT: ld s0, %lo(gd)(a1)
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; RV64FINX-NEXT: #APP
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; RV64FINX-NEXT: fadd.d t1, a0, s0
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; RV64FINX-NEXT: #NO_APP
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; RV64FINX-NEXT: mv a0, t1
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; RV64FINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
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; RV64FINX-NEXT: addi sp, sp, 16
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; RV64FINX-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "={t1},{a0},{s0}"(double %a, double %1)
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ret double %2
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}
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define double @constraint_f_double(double %a) nounwind {
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; RV32FINX-LABEL: constraint_f_double:
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; RV32FINX: # %bb.0:
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; RV32FINX-NEXT: lui a2, %hi(gd)
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; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2)
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; RV32FINX-NEXT: lw a2, %lo(gd)(a2)
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; RV32FINX-NEXT: #APP
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; RV32FINX-NEXT: fadd.d a0, a0, a2
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; RV32FINX-NEXT: #NO_APP
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; RV32FINX-NEXT: ret
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;
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; RV64FINX-LABEL: constraint_f_double:
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; RV64FINX: # %bb.0:
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; RV64FINX-NEXT: lui a1, %hi(gd)
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; RV64FINX-NEXT: ld a1, %lo(gd)(a1)
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; RV64FINX-NEXT: #APP
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; RV64FINX-NEXT: fadd.d a0, a0, a1
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; RV64FINX-NEXT: #NO_APP
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; RV64FINX-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
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ret double %2
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}
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define double @constraint_cf_double(double %a) nounwind {
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; RV32FINX-LABEL: constraint_cf_double:
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; RV32FINX: # %bb.0:
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; RV32FINX-NEXT: lui a2, %hi(gd)
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; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2)
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; RV32FINX-NEXT: lw a2, %lo(gd)(a2)
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; RV32FINX-NEXT: #APP
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; RV32FINX-NEXT: fadd.d a0, a0, a2
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; RV32FINX-NEXT: #NO_APP
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; RV32FINX-NEXT: ret
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;
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; RV64FINX-LABEL: constraint_cf_double:
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; RV64FINX: # %bb.0:
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; RV64FINX-NEXT: lui a1, %hi(gd)
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; RV64FINX-NEXT: ld a1, %lo(gd)(a1)
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; RV64FINX-NEXT: #APP
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; RV64FINX-NEXT: fadd.d a0, a0, a1
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; RV64FINX-NEXT: #NO_APP
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; RV64FINX-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "=^cf,^cf,^cf"(double %a, double %1)
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ret double %2
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}
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