7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
54 lines
1.6 KiB
LLVM
54 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s | FileCheck %s
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; Negative test
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define void @single_fdiv(double %a0, double %a1, ptr %res) {
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; CHECK-LABEL: single_fdiv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fdiv.d fa5, fa1, fa0
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; CHECK-NEXT: fsd fa5, 0(a0)
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; CHECK-NEXT: ret
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entry:
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%div = fdiv arcp double %a1, %a0
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store double %div, ptr %res
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ret void
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}
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define void @two_fdivs(double %a0, double %a1, double %a2, ptr %res) {
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; CHECK-LABEL: two_fdivs:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, %hi(.LCPI1_0)
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; CHECK-NEXT: fld fa5, %lo(.LCPI1_0)(a1)
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; CHECK-NEXT: fdiv.d fa5, fa5, fa0
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; CHECK-NEXT: fmul.d fa4, fa1, fa5
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; CHECK-NEXT: fmul.d fa5, fa2, fa5
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; CHECK-NEXT: fsd fa4, 0(a0)
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; CHECK-NEXT: fsd fa5, 8(a0)
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; CHECK-NEXT: ret
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entry:
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%div = fdiv arcp double %a1, %a0
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%div1 = fdiv arcp double %a2, %a0
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store double %div, ptr %res
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%arrayidx2 = getelementptr inbounds double, ptr %res, i64 1
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store double %div1, ptr %arrayidx2
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ret void
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}
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; Negative test
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define void @no_arcp(double %a0, double %a1, double %a2, ptr %res) {
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; CHECK-LABEL: no_arcp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fdiv.d fa5, fa1, fa0
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; CHECK-NEXT: fdiv.d fa4, fa2, fa0
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; CHECK-NEXT: fsd fa5, 0(a0)
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; CHECK-NEXT: fsd fa4, 8(a0)
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; CHECK-NEXT: ret
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entry:
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%div = fdiv arcp double %a1, %a0
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%div1 = fdiv double %a2, %a0
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store double %div, ptr %res
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%arrayidx2 = getelementptr inbounds double, ptr %res, i64 1
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store double %div1, ptr %arrayidx2
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ret void
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}
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