7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
21 lines
738 B
LLVM
21 lines
738 B
LLVM
; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
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; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
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; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s
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; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \
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; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s
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; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension
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define float @foo(i32 %a) nounwind #0 {
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; RV32IF-ILP32: fcvt.s.w fa5, a0
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; RV32IF-ILP32-NEXT: fmv.x.w a0, fa5
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; RV32IF-ILP32F: fcvt.s.w fa0, a0
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; RV32IF-ILP32F-NEXT: ret
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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attributes #0 = { "target-features"="+f"}
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