8624075105
The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.
32 lines
1.3 KiB
LLVM
32 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -start-after codegenprepare -mtriple=riscv64 -mattr=-v -o - %s | FileCheck --check-prefix=CHECK-NOV %s
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; RUN: llc -start-after codegenprepare -mtriple=riscv64 -mattr=+v -o - %s | FileCheck --check-prefix=CHECK-V %s
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; Reproducer for https://github.com/llvm/llvm-project/issues/55168.
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; We should always return 1 (and not -1).
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define i32 @test(i32 %call.i) {
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; CHECK-NOV-LABEL: test:
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; CHECK-NOV: # %bb.0:
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; CHECK-NOV-NEXT: li a0, 1
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; CHECK-NOV-NEXT: ret
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;
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; CHECK-V-LABEL: test:
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; CHECK-V: # %bb.0:
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; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-V-NEXT: vslide1down.vx v8, v8, a0
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; CHECK-V-NEXT: lui a0, 524288
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; CHECK-V-NEXT: vslide1down.vx v8, v8, a0
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; CHECK-V-NEXT: addi a0, a0, 2
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; CHECK-V-NEXT: vmslt.vx v0, v8, a0
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; CHECK-V-NEXT: vmv.v.i v8, 0
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; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
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; CHECK-V-NEXT: vmv.x.s a0, v8
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; CHECK-V-NEXT: ret
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%t2 = insertelement <2 x i32> <i32 poison, i32 -2147483648>, i32 %call.i, i64 0
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%t3 = icmp slt <2 x i32> %t2, <i32 -2147483646, i32 -2147483646>
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%t4 = zext <2 x i1> %t3 to <2 x i32>
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%t6 = extractelement <2 x i32> %t4, i64 1
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ret i32 %t6
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}
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