5ffbdd9ed5
Vector pseudos with scalar operands only use the lower SEW bits (or less in the case of shifts and clips). This patch accounts for this in hasAllNBitUsers for both SDNodes in RISCVISelDAGToDAG. We also need to handle this in RISCVOptWInstrs otherwise we introduce slliw instructions that are less compressible than their original slli counterpart. This is a reland of aff6ffc8760b99cc3d66dd6e251a4f90040c0ab9 with the refactoring omitted.
187 lines
7.7 KiB
LLVM
187 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s
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; Integers
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define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
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; CHECK-LABEL: vector_deinterleave_v16i1_v32i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: vadd.vv v11, v9, v9
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; CHECK-NEXT: vrgather.vv v9, v10, v11
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; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
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; CHECK-NEXT: vslidedown.vi v0, v0, 2
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: vadd.vi v12, v11, -16
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; CHECK-NEXT: li a0, -256
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; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
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; CHECK-NEXT: vrgather.vv v9, v8, v12, v0.t
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; CHECK-NEXT: vmsne.vi v9, v9, 0
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; CHECK-NEXT: vadd.vi v12, v11, 1
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; CHECK-NEXT: vrgather.vv v13, v10, v12
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; CHECK-NEXT: vadd.vi v10, v11, -15
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; CHECK-NEXT: vrgather.vv v13, v8, v10, v0.t
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; CHECK-NEXT: vmsne.vi v8, v13, 0
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; CHECK-NEXT: vmv.v.v v0, v9
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; CHECK-NEXT: ret
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%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
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ret {<16 x i1>, <16 x i1>} %retval
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}
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define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
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; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vnsrl.wi v11, v8, 8
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: vmv.v.v v9, v11
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; CHECK-NEXT: ret
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%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
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ret {<16 x i8>, <16 x i8>} %retval
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}
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define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
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; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vnsrl.wi v11, v8, 16
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: vmv.v.v v9, v11
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; CHECK-NEXT: ret
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%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
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ret {<8 x i16>, <8 x i16>} %retval
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}
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define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4i32_vv8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wx v10, v8, a0
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; CHECK-NEXT: vnsrl.wi v11, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v11
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; CHECK-NEXT: vmv.v.v v9, v10
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; CHECK-NEXT: ret
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%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
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ret {<4 x i32>, <4 x i32>} %retval
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}
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define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v10, v8, 2
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.i v0, 2
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vrgather.vi v9, v8, 1
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; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
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; CHECK-NEXT: vslideup.vi v8, v10, 1
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; CHECK-NEXT: ret
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%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
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ret {<2 x i64>, <2 x i64>} %retval
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}
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declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>)
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declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
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declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
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declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>)
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declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>)
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; Floats
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define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vnsrl.wi v9, v8, 16
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
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ret {<2 x half>, <2 x half>} %retval
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}
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define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vnsrl.wi v9, v8, 16
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
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ret {<4 x half>, <4 x half>} %retval
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}
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define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wx v9, v8, a0
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
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ret {<2 x float>, <2 x float>} %retval
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}
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define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vnsrl.wi v11, v8, 16
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: vmv.v.v v9, v11
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; CHECK-NEXT: ret
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%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
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ret {<8 x half>, <8 x half>} %retval
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}
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define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wx v10, v8, a0
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; CHECK-NEXT: vnsrl.wi v11, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v11
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; CHECK-NEXT: vmv.v.v v9, v10
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; CHECK-NEXT: ret
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%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
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ret {<4 x float>, <4 x float>} %retval
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}
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define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v10, v8, 2
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.i v0, 2
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vrgather.vi v9, v8, 1
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; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
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; CHECK-NEXT: vslideup.vi v8, v10, 1
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; CHECK-NEXT: ret
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%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
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ret {<2 x double>, <2 x double>} %retval
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}
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declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
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declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
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declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
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declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
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declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
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declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)
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