8765ad42cd
This patch simplifies the switch statement in getInstruction to add implicit operands (register ZA and Immediate equal to zero) in the SME operands when disassembly. The register ZA and the zero immediate can be added by checking the operand in MCInstDesc. Differential Revision: https://reviews.llvm.org/D125534
38 lines
1.3 KiB
C++
38 lines
1.3 KiB
C++
//===- AArch64Disassembler.h - Disassembler for AArch64 ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64DISASSEMBLER_H
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#define LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64DISASSEMBLER_H
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInstrInfo.h"
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namespace llvm {
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class AArch64Disassembler : public MCDisassembler {
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std::unique_ptr<const MCInstrInfo> const MCII;
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public:
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AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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~AArch64Disassembler() override = default;
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MCDisassembler::DecodeStatus
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getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
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uint64_t Address, raw_ostream &CStream) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64DISASSEMBLER_H
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