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llvm-project/llvm/test/CodeGen/RISCV/rvv
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jacquesguan e60eb7053d recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat." 
With fix for AArch64 and Hexgon test cases.
2022-07-21 17:34:34 +08:00
..
abs-sdnode.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
access-fixed-objects-by-rvv.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
active_lane_mask.ll
[RISCV] Mark vsadd(u)_vl as commutable
2022-07-08 10:18:21 -07:00
addi-rvv-stack-object.mir
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
addi-scalable-offset.mir
[RISCV][NFC] Update testcase for D126861
2022-06-10 00:18:02 +08:00
aliases.mir
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
allocate-lmul-2-4-8.ll
[RISCV] Extend use of SHXADD instructions in RVV spill/reload code.
2022-07-18 10:53:19 +08:00
allone-masked-to-unmasked.ll
[RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process
2022-04-26 20:14:54 -07:00
bitreverse-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
bswap-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
calling-conv-fastcc.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
calling-conv.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
cmp-folds.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
combine-sats.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
combine-splats.ll
[SelectionDAG] Add SPLAT_VECTOR to SelectionDAG::isConstantFPBuildVectorOrConstantFP.
2022-02-16 09:22:11 -08:00
combine-store-fp.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
common-shuffle-patterns.ll
[RISCV] Add more types of shuffles isShuffleMaskLegal.
2022-02-04 09:13:13 -08:00
commuted-op-indices-regression.mir
[RISCV] Print human-readable VTYPE/SEW/LMUL in MIR
2022-04-22 17:13:18 +01:00
constant-folding-crash.ll
Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
2022-06-29 10:27:02 -07:00
constant-folding.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
ctlz-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
ctpop-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
cttz-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
debug-info-rvv-dbg-value.mir
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
emergency-slot.mir
[RISCV] Use two ADDIs to do some stack pointer adjustments.
2022-05-31 10:25:28 -07:00
extload-truncstore.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
extract-subvector.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
extractelt-fp-rv32.ll
[RISCV][test] Add test of binop followed by extractelement.
2022-07-13 14:33:56 +08:00
extractelt-fp-rv64.ll
[RISCV][test] Add test of binop followed by extractelement.
2022-07-13 14:33:56 +08:00
extractelt-i1.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
extractelt-int-rv32.ll
[RISCV][test] Add test of binop followed by extractelement.
2022-07-13 14:33:56 +08:00
extractelt-int-rv64.ll
[RISCV][test] Add test of binop followed by extractelement.
2022-07-13 14:33:56 +08:00
fceil-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
ffloor-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
fixed-vector-fpext-vp.ll
[LegalizeTypes][VP] Add widen and split support for vp.fptrunc and vp.fpext
2022-06-06 02:28:01 +00:00
fixed-vector-fptrunc-vp.ll
[LegalizeTypes][VP] Add widen and split support for vp.fptrunc and vp.fpext
2022-06-06 02:28:01 +00:00
fixed-vector-segN-load.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vector-strided-load-store-asm.ll
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
fixed-vector-strided-load-store-negative.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vector-strided-load-store.ll
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
fixed-vector-trunc-vp-mask.ll
[RISCV][VP] Add RVV codegen for vp.trunc.
2022-04-15 02:29:53 +00:00
fixed-vector-trunc-vp.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-abs.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-bitcast-large-vector.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-bitcast.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-bitreverse.ll
[RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
2022-06-16 11:14:21 -07:00
fixed-vectors-bswap.ll
[RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
2022-06-16 11:14:21 -07:00
fixed-vectors-calling-conv-fastcc.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-calling-conv.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-ctlz.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-ctpop.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-cttz.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
fixed-vectors-elen.ll
[RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option.
2022-04-11 10:14:48 -07:00
fixed-vectors-emergency-slot.mir
[RISCV] Ensure the entire stack is aligned to the RVV stack alignment
2022-05-24 06:58:51 +01:00
fixed-vectors-extload-truncstore.ll
[RISCV] Move store policy and mask reg ops into demanded handling in InsertVSETVLI
2022-06-17 12:09:50 -07:00
fixed-vectors-extract-i1.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-extract-subvector.ll
[IR] Move vector.insert/vector.extract out of experimental namespace
2022-06-27 10:48:45 +00:00
fixed-vectors-extract.ll
[RISCV][test] Add test of binop followed by extractelement.
2022-07-13 14:33:56 +08:00
fixed-vectors-fp2i.ll
Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
2022-06-29 10:27:02 -07:00
fixed-vectors-fp-bitcast.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
fixed-vectors-fp-buildvec.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-fp-conv.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-fp-interleave.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-fp-setcc.ll
Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
2022-06-29 10:27:02 -07:00
fixed-vectors-fp-shuffles.ll
[RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
2022-06-16 11:14:21 -07:00
fixed-vectors-fp-splat.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-fp-vrgather.ll
[RISCV] Use the new chain when converting a fixed RVV load
2022-05-13 22:21:08 +00:00
fixed-vectors-fp.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-fptosi-vp-mask.ll
[RISCV] Add support for vp.fptosi where the result is a mask type.
2022-04-05 09:48:04 -07:00
fixed-vectors-fptosi-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
fixed-vectors-fptoui-vp-mask.ll
[RISCV] Add support for vp.fptosi where the result is a mask type.
2022-04-05 09:48:04 -07:00
fixed-vectors-fptoui-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
fixed-vectors-i2fp.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-insert-i1.ll
[DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfere
2022-06-13 11:48:18 +01:00
fixed-vectors-insert-subvector.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-insert.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
fixed-vectors-int-buildvec.ll
[RISCV] Move creation of constant pools from isel to lowering.
2022-06-13 09:07:57 -07:00
fixed-vectors-int-exttrunc.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-int-interleave.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-int-setcc.ll
[RISCV][2/3] Switch undef -> poison in fixed-vector RVV tests
2022-02-01 11:06:56 +00:00
fixed-vectors-int-shuffles.ll
[RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
2022-06-16 11:14:21 -07:00
fixed-vectors-int-splat.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-int-vrgather.ll
[RISCV] Use the new chain when converting a fixed RVV load
2022-05-13 22:21:08 +00:00
fixed-vectors-int.ll
[RISCV] Mark (s/u)min_vl and (s/u)max_vl as commutable.
2022-07-08 09:59:42 -07:00
fixed-vectors-marith-vp.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-mask-buildvec.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-mask-load-store.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
fixed-vectors-mask-logic.ll
[RISCV] Fix alias printing for vmnot.m
2022-04-28 08:33:52 -07:00
fixed-vectors-mask-splat.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
fixed-vectors-masked-gather.ll
[RISCV] Optimize (brcond (seteq (and X, 1 << C), 0))
2022-07-20 18:40:49 -07:00
fixed-vectors-masked-load-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-masked-load-int.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-masked-scatter.ll
[RISCV] Optimize (brcond (seteq (and X, 1 << C), 0))
2022-07-20 18:40:49 -07:00
fixed-vectors-masked-store-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-masked-store-int.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-reduction-fp-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-reduction-fp.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-reduction-int-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-reduction-int.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
fixed-vectors-reduction-mask-vp.ll
[RISCV] Support VP_REDUCE_MUL mask operation
2022-05-30 03:05:39 +00:00
fixed-vectors-select-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-select-int.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-setcc-fp-vp.ll
[RISCV][VP] Add fp test of widen and split for vp.setcc
2022-06-09 08:14:12 +00:00
fixed-vectors-setcc-int-vp-mask.ll
[RISCV] Support VP_SETCC mask operations
2022-04-28 08:52:29 +00:00
fixed-vectors-setcc-int-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-sext-vp-mask.ll
[RISCV] Add lowering for vp.sext and vp.zext.
2022-04-06 09:59:49 -07:00
fixed-vectors-sext-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP_SIGN_EXTEND and VP_ZERO_EXTEND.
2022-06-02 02:21:22 +00:00
fixed-vectors-sitofp-vp-mask.ll
[RISCV] Add lowering for vp.fptosi and vp.sitofp.
2022-03-28 11:06:41 -07:00
fixed-vectors-sitofp-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
fixed-vectors-stepvector-rv32.ll
[RISCV][test] Add widen STEP_VECTOR tests.
2022-06-09 07:47:04 +00:00
fixed-vectors-stepvector-rv64.ll
[RISCV][test] Add widen STEP_VECTOR tests.
2022-06-09 07:47:04 +00:00
fixed-vectors-store-merge-crash.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
fixed-vectors-uitofp-vp-mask.ll
[RISCV] Add lowering for vp.fptoui and vp.uitofp.
2022-04-01 18:28:46 -07:00
fixed-vectors-uitofp-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
fixed-vectors-unaligned.ll
[RISCV] Pre-promote v1i1/v2i1/v4i1->i1/i2/i4 bitcasts before type legalization
2022-06-18 11:06:45 -07:00
fixed-vectors-vadd-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vand-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vdiv-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vdivu-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vfadd-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfdiv-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfma-vp.ll
[RISCV] Use TAIL_AGNOSTIC in riscv_fma_vl patterns.
2022-06-16 09:09:36 -07:00
fixed-vectors-vfmax.ll
[RISCV] Mark fminnum_vl and fmaxnum_vl as commutable.
2022-07-08 10:19:09 -07:00
fixed-vectors-vfmin.ll
[RISCV] Mark fminnum_vl and fmaxnum_vl as commutable.
2022-07-08 10:19:09 -07:00
fixed-vectors-vfmul-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfneg-vp.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfsub-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vfwadd.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vfwmacc.ll
[RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions.
2022-05-20 06:56:48 +00:00
fixed-vectors-vfwmul.ll
[RISCV] Add VL patterns for vfwmul/vfwadd/vfwsub
2022-03-31 07:08:58 +00:00
fixed-vectors-vfwsub.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vmul-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vnsra-vnsrl.ll
[RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL.
2022-05-24 21:38:59 -07:00
fixed-vectors-vor-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vpgather.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
fixed-vectors-vpload.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vpmerge.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vpscatter.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
fixed-vectors-vpstore.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vreductions-mask.ll
[RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation
2022-05-19 09:53:33 +00:00
fixed-vectors-vrem-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vremu-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vrsub-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vsadd.ll
[RISCV] Mark vsadd(u)_vl as commutable
2022-07-08 10:18:21 -07:00
fixed-vectors-vsaddu.ll
[RISCV] Mark vsadd(u)_vl as commutable
2022-07-08 10:18:21 -07:00
fixed-vectors-vselect-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vselect.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
fixed-vectors-vshl-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
fixed-vectors-vsra-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
fixed-vectors-vsrl-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
fixed-vectors-vssub.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vssubu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vsub-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-vwadd.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwaddu.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwmacc.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
fixed-vectors-vwmaccsu.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
fixed-vectors-vwmaccu.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
fixed-vectors-vwmaccus.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
fixed-vectors-vwmul.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwmulsu.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwmulu.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwsub.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vwsubu.ll
[RISCV] Extend demanded field transform in InsertVSETVLI to VTYPE subfeilds
2022-06-16 08:01:27 -07:00
fixed-vectors-vxor-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fixed-vectors-zext-vp-mask.ll
[RISCV] Add lowering for vp.sext and vp.zext.
2022-04-06 09:59:49 -07:00
fixed-vectors-zext-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP_SIGN_EXTEND and VP_ZERO_EXTEND.
2022-06-02 02:21:22 +00:00
fold-binary-reduce.ll
[RISCV] Add DAGCombine to fold base operation and reduction.
2022-04-30 14:07:05 +08:00
fptosi-sat.ll
[SelectionDAG] Fix fptoi.sat scalable vector lowering
2022-07-21 08:00:22 +01:00
fptoui-sat.ll
[SelectionDAG] Fix fptoi.sat scalable vector lowering
2022-07-21 08:00:22 +01:00
frameindex-addr.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fround-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
fshr-fshl.ll
[RISCV] Add basic fshr/fshl cost and codegen coverage
2022-06-13 11:49:53 -07:00
ftrunc-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
get-vlen-debugloc.mir
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
implicit-def-copy.ll
[SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources.
2022-06-16 14:55:14 -07:00
inline-asm.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
insert-subvector.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
insertelt-fp-rv32.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
insertelt-fp-rv64.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
insertelt-i1.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
insertelt-int-rv32.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
insertelt-int-rv64.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
interleave-crash.ll
[RISCV] Add more types of shuffles isShuffleMaskLegal.
2022-02-04 09:13:13 -08:00
large-rvv-stack-size.mir
[RISCV] Use two ADDIs to do some stack pointer adjustments.
2022-05-31 10:25:28 -07:00
legalize-load-sdnode.ll
[DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses
2022-05-17 13:40:11 +01:00
legalize-scalable-vectortype.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
legalize-store-sdnode.ll
[DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses
2022-05-17 13:40:11 +01:00
load-add-store-8.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
load-add-store-16.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
load-add-store-32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
load-add-store-64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
load-mask.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
localvar.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
marith-vp.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
mask-exts-truncs-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
mask-exts-truncs-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
mask-reg-alloc.mir
[RISCV] Print human-readable VTYPE/SEW/LMUL in MIR
2022-04-22 17:13:18 +01:00
masked-load-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
masked-load-int.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
masked-store-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
masked-store-int.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
masked-tama.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
masked-tamu.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
masked-tuma.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
masked-tumu.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
masked-vslide1down-rv32.ll
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
memory-args.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
mgather-sdnode.ll
[IR] Move vector.insert/vector.extract out of experimental namespace
2022-06-27 10:48:45 +00:00
mscatter-sdnode.ll
[IR] Move vector.insert/vector.extract out of experimental namespace
2022-06-27 10:48:45 +00:00
named-vector-shuffle-reverse.ll
[RISCV] Support VECTOR_REVERSE mask operation.
2022-06-28 07:48:51 +00:00
no-reserved-frame.ll
[RISCV] Ensure the entire stack is aligned to the RVV stack alignment
2022-05-24 06:58:51 +01:00
pass-fast-math-flags-sdnode.ll
[RISCV] Preserve fast math flags in lowerVPOp.
2022-05-25 09:16:07 -07:00
pr52475.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
reg-alloc-reserve-bp.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
reg-coalescing.mir
[RISCV] Print human-readable VTYPE/SEW/LMUL in MIR
2022-04-22 17:13:18 +01:00
regalloc-fast-crash.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
rv32-spill-vector-csr.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
rv32-spill-vector.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
rv32-spill-zvlsseg.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
rv32-vsetvli-intrinsics.ll
[riscv] Use X0 for destination of VSETVLI instruction if result unused
2022-05-05 07:39:45 -07:00
rv64-spill-vector-csr.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
rv64-spill-vector.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
rv64-spill-zvlsseg.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
rv64-vsetvli-intrinsics.ll
[riscv] Use X0 for destination of VSETVLI instruction if result unused
2022-05-05 07:39:45 -07:00
rvv-args-by-mem.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
rvv-framelayout.ll
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
rvv-out-arguments.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
rvv-stack-align.mir
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
rvv-vscale.i32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
rvv-vscale.i64.ll
[RISCV] Refine known bits for READ_VLENB
2022-06-28 15:42:14 -07:00
saddo-sdnode.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
scalar-stack-align.ll
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
select-fp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
select-int.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
select-sra.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
setcc-fp-vp.ll
[RISCV][VP] Add fp test of widen and split for vp.setcc
2022-06-09 08:14:12 +00:00
setcc-fp.ll
[RISCV] Fix incorrect use of tail agnostic vslideup.
2022-05-15 18:32:21 -07:00
setcc-int-vp-mask.ll
[RISCV] Support VP_SETCC mask operations
2022-04-28 08:52:29 +00:00
setcc-int-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
setcc-integer.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
sink-splat-operands.ll
[LSR] Allow already invariant operand for ICmpZero matching [try 2]
2022-07-15 13:29:43 -07:00
smulo-sdnode.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
splat-vectors.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
stack-coloring-scalablevec.mir
[StackColoring] Don't merge slots with differing StackIDs
2022-05-17 08:28:49 +01:00
stepvector.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
tail-agnostic-impdef-copy.mir
[RISCV] Print human-readable VTYPE/SEW/LMUL in MIR
2022-04-22 17:13:18 +01:00
umulo-sdnode.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
unaligned-loads-stores.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
undef-subreg-range.mir
[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
2022-06-15 16:23:39 +08:00
undef-vp-ops.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
unmasked-ta.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
unmasked-tu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
urem-seteq-vec.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vaadd.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vaaddu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vadc-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vadc-rv64.ll
[RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.
2022-02-17 02:21:39 -08:00
vadd-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vadd-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vadd.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vand-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vand-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vand-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vand-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vasub.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vasubu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vcompress.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vcpop.ll
[RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm
2022-02-25 14:44:25 +08:00
vdiv-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vdiv-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vdiv-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vdiv-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vdivu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vdivu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vdivu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vdivu-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vector-splice.ll
[RISCV] Change VECTOR_SPLICE mask operation from expand to promote
2022-07-08 06:20:22 +00:00
vexts-sdnode.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vfabs-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
vfadd-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfadd-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfadd.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfclass.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcopysign-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-f-x.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-f-xu.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-rtz-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-rtz-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfcvt-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfdiv-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfdiv-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfdiv.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfirst.ll
[RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm
2022-02-25 14:44:25 +08:00
vfma-vp.ll
[RISCV] Move vfma_vl+fneg_vl matching to DAG combine.
2022-06-24 00:00:37 -07:00
vfmacc.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmadd-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmadd.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmax-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmax.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmerge.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmin-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmin.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmsac.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmsub-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmsub.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmul-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmul-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmul.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmv.f.s.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmv.s.f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfmv.v.f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-f-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-f-x.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-f-xu.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-rod-f-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-rtz-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-rtz-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfncvt-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfneg-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
vfneg-vp.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
vfnmacc.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfnmadd-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfnmadd.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfnmsac.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfnmsub-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfnmsub.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfpext-sdnode.ll
[RISCV][NFC] Add common check prefix to reduce duplicate check lines.
2022-03-22 11:06:52 +08:00
vfpext-vp.ll
[LegalizeTypes][VP] Add widen and split support for vp.fptrunc and vp.fpext
2022-06-06 02:28:01 +00:00
vfptoi-sdnode.ll
[LegalizeTypes][VP] Add integer promotion support for vp.fptosi/vp.fptoui
2022-05-30 03:05:39 +00:00
vfptosi-vp-mask.ll
[RISCV] Add support for vp.fptosi where the result is a mask type.
2022-04-05 09:48:04 -07:00
vfptosi-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
vfptoui-vp-mask.ll
[RISCV] Add support for vp.fptosi where the result is a mask type.
2022-04-05 09:48:04 -07:00
vfptoui-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
vfptrunc-sdnode.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
vfptrunc-vp.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vfrdiv-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfrdiv.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfrec7.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfredmax.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfredmin.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfredosum.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfredusum.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfrsqrt7.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfrsub-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfrsub.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsgnj.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsgnjn.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsgnjx.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfslide1down.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfslide1up.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsqrt-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsqrt.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsub-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsub-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfsub.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwadd-sdnode.ll
[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
2022-04-01 03:09:50 +00:00
vfwadd.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwadd.w.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-f-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-f-x.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-f-xu.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-rtz-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-rtz-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-x-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwcvt-xu-f.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwmacc-sdnode.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwmacc.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwmsac.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwmul-sdnode.ll
[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
2022-04-01 03:09:50 +00:00
vfwmul.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwnmacc.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwnmsac.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwredosum.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwredusum.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwsub-sdnode.ll
[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
2022-04-01 03:09:50 +00:00
vfwsub.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vfwsub.w.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vid.ll
[RISCV] Add policy operand for masked vid and viota IR intrinsics.
2022-03-22 02:32:31 -07:00
viota.ll
[RISCV] Add policy operand for masked vid and viota IR intrinsics.
2022-03-22 02:32:31 -07:00
vitofp-sdnode.ll
[LegalizeTypes][VP] Add integer promotion support for vp.sitofp/vp.uitofp
2022-05-22 02:13:45 +00:00
vle.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vleff-rv32.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vleff-rv64.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vleff-vlseg2ff-output.ll
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
vlm.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vloxei-rv64.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vloxei.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vloxseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vloxseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlse.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vlseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsegff-rv32-dead.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsegff-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsegff-rv64-dead.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsegff-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vlsseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vluxei-rv64.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vluxei.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vluxseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vluxseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vmacc-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmacc-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vmadc-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmadc-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmadc.carry.in-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmadc.carry.in-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmadd-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmadd-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vmadd-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmand.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmandn.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmarith-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vmax-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmax-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vmax-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmaxu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmaxu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vmaxu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmclr.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmerge.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vmfeq.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmfge.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmfgt.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmfle.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmflt.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmfne.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmin-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmin-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vmin-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vminu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vminu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vminu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmnand.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmnor.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmor.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmorn.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmsbc-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsbc-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmsbc.borrow.in-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsbc.borrow.in-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmsbf.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmseq-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmseq-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmset.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmsge-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsge-rv64.ll
[RISCV] Fix alias printing for vmnot.m
2022-04-28 08:33:52 -07:00
vmsgeu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsgeu-rv64.ll
[RISCV] Fix alias printing for vmnot.m
2022-04-28 08:33:52 -07:00
vmsgt-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsgt-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsgtu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsgtu-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsif.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsle-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsle-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsleu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsleu-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmslt-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmslt-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsltu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsltu-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsne-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmsne-rv64.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmsof.ll
Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"
2022-03-29 18:05:33 -07:00
vmul-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vmul-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmul.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmulh-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vmulh.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmulhsu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmulhu-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vmulhu.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmv-copy.mir
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
vmv.s.x-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmv.s.x-rv64.ll
[RISCV] Fix incorrect codegen introduced by D119688.
2022-03-05 06:10:26 -08:00
vmv.v.v-rv32.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vmv.v.v-rv64.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vmv.v.x-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vmv.v.x-rv64.ll
[RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics.
2022-02-17 06:38:14 -08:00
vmv.x.s-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmv.x.s-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vmxnor.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vmxor.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vnclip.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vnclipu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vnmsac-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vnmsac-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vnmsub-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vnmsub-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vnmsub-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vnsra-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vnsra-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vnsra-sdnode.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
vnsrl-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vnsrl-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vnsrl-sdnode.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
vor-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vor-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vor-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vor-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vpgather-sdnode.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vpload.ll
[IR] Move vector.insert/vector.extract out of experimental namespace
2022-06-27 10:48:45 +00:00
vpmerge-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vpscatter-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
vpstore.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vredand-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredand-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmax-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmax-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmaxu-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmaxu-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmin-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredmin-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredminu-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredminu-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredor-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredor-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredsum-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredsum-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vreductions-fp-sdnode.ll
[SelectionDAG] Enable WidenVecOp_VECREDUCE for scalable vector
2022-06-24 02:32:53 +00:00
vreductions-fp-vp.ll
[RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll
2022-06-17 02:22:59 +00:00
vreductions-int-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vreductions-int.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vreductions-mask-vp.ll
[RISCV] Support VP_REDUCE_MUL mask operation
2022-05-30 03:05:39 +00:00
vreductions-mask.ll
[RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation
2022-05-19 09:53:33 +00:00
vredxor-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vredxor-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vrem-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vrem-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vrem-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vrem-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vremu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vremu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vremu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vremu-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vrgather-rv32.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vrgather-rv64.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vrgatherei16-rv32.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vrgatherei16-rv64.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vrgatherei16-subreg-liveness.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vrsub-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vrsub-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vrsub.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsadd-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsadd-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsadd-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsaddu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsaddu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsaddu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsbc-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsbc-rv64.ll
[RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.
2022-02-17 02:21:39 -08:00
vscale-power-of-two.ll
[RISCV] Exploit fact that vscale is always power of two to replace urem sequence
2022-07-13 10:54:47 -07:00
vse.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vselect-fp-rv32.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vselect-fp-rv64.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vselect-int-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vselect-int-rv64.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vselect-mask.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vselect-vp.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
vsetvl-ext.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vsetvli-insert-crossbb.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vsetvli-insert-crossbb.mir
[RISCV] Fix an inconsistency with compatible load/store handling
2022-06-02 08:03:51 -07:00
vsetvli-insert.ll
[RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF.
2022-06-15 13:58:40 +08:00
vsetvli-insert.mir
[RISCV] Add a test covering a (reverted) codegen issue
2022-06-30 09:27:52 +01:00
vsetvli-regression.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vsext-vp-mask.ll
[RISCV] Add lowering for vp.sext and vp.zext.
2022-04-06 09:59:49 -07:00
vsext-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP_SIGN_EXTEND and VP_ZERO_EXTEND.
2022-06-02 02:21:22 +00:00
vsext.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vshl-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vshl-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
vsitofp-vp-mask.ll
[RISCV] Add lowering for vp.fptosi and vp.sitofp.
2022-03-28 11:06:41 -07:00
vsitofp-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
vslide1down-constant-vl-rv32.ll
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
vslide1down-rv32.ll
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
vslide1down-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vslide1up-constant-vl-rv32.ll
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
vslide1up-rv32.ll
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
vslide1up-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vslidedown-rv32.ll
[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
2022-04-25 09:18:41 -07:00
vslidedown-rv64.ll
[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
2022-04-25 09:18:41 -07:00
vslideup-rv32.ll
[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
2022-04-25 09:18:41 -07:00
vslideup-rv64.ll
[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
2022-04-25 09:18:41 -07:00
vsll-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsll-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsm.ll
[RISCV] Merge some rvv intrinsic test cases that only differ by XLen type.
2022-01-22 21:55:29 -08:00
vsmul-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsmul-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsoxei-rv64.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vsoxei.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vsoxseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vsoxseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vsplats-fp.ll
[RISCV][NFC] Add common check prefix to reduce duplicate check lines.
2022-03-22 11:06:52 +08:00
vsplats-i1.ll
[RISCV] Disable matchSplatAsGather for i1 vectors to prevent creating illegal nodes.
2022-06-13 13:41:39 -07:00
vsplats-i64.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsra-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsra-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsra-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vsra-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
vsrl-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsrl-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vsrl-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vsrl-vp.ll
[RISCV][1/3] Switch undef -> poison in VP RVV tests
2022-02-01 11:06:55 +00:00
vsse.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vsseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vsseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vssra-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssra-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssrl-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssrl-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vssseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vssub-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vssub-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssub-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vssubu-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vssubu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vssubu-sdnode.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsub-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vsub-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsub.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vsuxei-rv64.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vsuxei.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
vsuxseg-rv32.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vsuxseg-rv64.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
vtrunc-vp-mask.ll
[RISCV][VP] Add RVV codegen for vp.trunc.
2022-04-15 02:29:53 +00:00
vtrunc-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP_TRUNCATE
2022-05-26 02:03:27 +00:00
vtruncs-sdnode.ll
[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.
2022-03-22 10:14:43 -07:00
vuitofp-vp-mask.ll
[RISCV] Add lowering for vp.fptoui and vp.uitofp.
2022-04-01 18:28:46 -07:00
vuitofp-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP FP integer casting op.
2022-06-02 09:05:27 +00:00
vwadd-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwadd-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwadd-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vwadd.w-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwadd.w-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwaddu-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwaddu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwaddu.w-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwaddu.w-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmacc-rv32.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmacc-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmacc-sdnode.ll
[RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
2022-04-06 03:18:01 +00:00
vwmaccsu-rv32.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmaccsu-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmaccu-rv32.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmaccu-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmaccus-rv32.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmaccus-rv64.ll
[RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.
2022-02-17 09:12:46 -08:00
vwmul-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmul-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmul-sdnode.ll
[RISCV] Add patterns for vector widening integer multiply
2022-03-24 15:26:08 +08:00
vwmulsu-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmulsu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmulu-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwmulu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwredsum-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vwredsum-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vwredsumu-rv32.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vwredsumu-rv64.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vwsub-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsub-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsub-sdnode.ll
[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests
2022-02-01 11:06:56 +00:00
vwsub.w-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsub.w-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsubu-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsubu-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsubu.w-rv32.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vwsubu.w-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vxor-rv32.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vxor-rv64.ll
[RISCV] Add the passthru operand for RVV nomask binary intrinsics.
2022-02-15 18:36:18 -08:00
vxor-sdnode.ll
recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."
2022-07-21 17:34:34 +08:00
vxor-vp.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
vzext-vp-mask.ll
[RISCV] Add lowering for vp.sext and vp.zext.
2022-04-06 09:59:49 -07:00
vzext-vp.ll
[LegalizeTypes][VP] Add widen and split support for VP_SIGN_EXTEND and VP_ZERO_EXTEND.
2022-06-02 02:21:22 +00:00
vzext.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-06-25 13:21:44 -07:00
wrong-chain-fixed-load.ll
[RISCV] Use the new chain when converting a fixed RVV load
2022-05-13 22:21:08 +00:00
wrong-stack-offset-for-rvv-object.mir
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
wrong-stack-slot-rv32.mir
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
wrong-stack-slot-rv64.mir
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
zve32-types.ll
[RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.
2022-06-23 08:49:18 -07:00
zvlsseg-copy.mir
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
zvlsseg-spill.mir
[RISCV] Print human-readable VTYPE/SEW/LMUL in MIR
2022-04-22 17:13:18 +01:00
zvlsseg-zero-vl.ll
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00