c06d0b4d02
RVV doesn't have immediate field for memory addressing. Currently we build MachineInstructions in PEI to computing stack offset for RVV load store instructions. These instructions were added too late to can be optimized by CSE, LICM... passes. This patch makes FrameIndex SDNodes can't be matched in RVV Load Store instruction selection patterns. So that the FrameIndex SDNodes would be selected as `ADDI GPR, targetframeindex`. There are 2 advantages for such change: 1. Stack objects address computing can be optimized by machine function passes. 2. Since the ADDI instruction's destination register can be used as a temp register, we can save an emergency spill slot. Differential Revision: https://reviews.llvm.org/D128187
78 lines
2.9 KiB
LLVM
78 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IV
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declare <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
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<vscale x 64 x i8>,
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<vscale x 64 x i8>,
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<vscale x 64 x i8>,
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i64,
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i64);
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define <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2) {
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; RV64IV-LABEL: callee:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: vl8r.v v24, (a0)
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; RV64IV-NEXT: li a0, 1024
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; RV64IV-NEXT: vsetvli zero, a0, e8, m8, tu, mu
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; RV64IV-NEXT: vmacc.vv v8, v16, v24
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; RV64IV-NEXT: ret
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%ret = call <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
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<vscale x 64 x i8> %arg0,
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<vscale x 64 x i8> %arg1,
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<vscale x 64 x i8> %arg2, i64 1024, i64 0)
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ret <vscale x 64 x i8> %ret
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}
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define <vscale x 64 x i8> @caller() {
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; RV64IV-LABEL: caller:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -80
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; RV64IV-NEXT: .cfi_def_cfa_offset 80
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; RV64IV-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
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; RV64IV-NEXT: .cfi_offset ra, -8
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; RV64IV-NEXT: .cfi_offset s0, -16
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; RV64IV-NEXT: addi s0, sp, 80
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; RV64IV-NEXT: .cfi_def_cfa s0, 0
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 5
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: andi sp, sp, -64
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: li a1, 24
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; RV64IV-NEXT: mul a0, a0, a1
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: addi a0, a0, 64
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; RV64IV-NEXT: vl8r.v v8, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 4
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: addi a0, a0, 64
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; RV64IV-NEXT: vl8r.v v16, (a0)
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 3
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; RV64IV-NEXT: add a0, sp, a0
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; RV64IV-NEXT: addi a0, a0, 64
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; RV64IV-NEXT: vl8r.v v24, (a0)
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; RV64IV-NEXT: addi a1, sp, 64
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; RV64IV-NEXT: addi a0, sp, 64
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; RV64IV-NEXT: vs8r.v v24, (a1)
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; RV64IV-NEXT: call callee@plt
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; RV64IV-NEXT: addi sp, s0, -80
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; RV64IV-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
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; RV64IV-NEXT: addi sp, sp, 80
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; RV64IV-NEXT: ret
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%local0 = alloca <vscale x 64 x i8>
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%local1 = alloca <vscale x 64 x i8>
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%local2 = alloca <vscale x 64 x i8>
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%arg0 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
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%arg1 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
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%arg2 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local2
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%ret = call <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0,
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<vscale x 64 x i8> %arg1,
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<vscale x 64 x i8> %arg2)
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ret <vscale x 64 x i8> %ret
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}
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