1e926a9f9c
Summary: This fixes some tests that did not specify -mcpu. Doing that disables all subtarget features, which gives behavior that (a) does not necessarily correspond to any actual target, and (b) can change as we add new subtarget features. Also added gfx1010 to memtime test. Differential Revision: https://reviews.llvm.org/D74594 Change-Id: I8c0fe4fa03e9a93ef8bb722cd42d22e064526309
154 lines
4.8 KiB
LLVM
154 lines
4.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}fold_sgpr:
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; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s
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define amdgpu_kernel void @fold_sgpr(i32 addrspace(1)* %out, i32 %fold) {
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entry:
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%tmp0 = icmp ne i32 %fold, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%offset = add i32 %fold, %id
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%tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
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store i32 0, i32 addrspace(1)* %tmp1
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_imm:
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; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
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define amdgpu_kernel void @fold_imm(i32 addrspace(1)* %out, i32 %cmp) {
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entry:
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%fold = add i32 3, 2
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%tmp0 = icmp ne i32 %cmp, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%val = or i32 %id, %fold
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store i32 %val, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_64bit_constant_add:
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; CHECK-NOT: s_mov_b64
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; FIXME: It would be better if we could use v_add here and drop the extra
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; v_mov_b32 instructions.
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; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
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; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
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; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
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; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
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; CHECK: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}},
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define amdgpu_kernel void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) {
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entry:
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%tmp0 = add i64 %val, 1
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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; Inline constants should always be folded.
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; CHECK-LABEL: {{^}}vector_inline:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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define amdgpu_kernel void @vector_inline(<4 x i32> addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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ret void
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}
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; Immediates with one use should be folded
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; CHECK-LABEL: {{^}}imm_one_use:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}
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define amdgpu_kernel void @imm_one_use(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = xor i32 %tmp0, 100
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}vector_imm:
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; CHECK: s_movk_i32 [[IMM:s[0-9]+]], 0x64
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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define amdgpu_kernel void @vector_imm(<4 x i32> addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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ret void
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}
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; A subregister use operand should not be tied.
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; CHECK-LABEL: {{^}}no_fold_tied_subregister:
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; CHECK: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; CHECK: v_mac_f32_e32 v[[LO]], 0x41200000, v[[HI]]
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; CHECK: buffer_store_dword v[[LO]]
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define amdgpu_kernel void @no_fold_tied_subregister() {
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%tmp1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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%tmp2 = extractelement <2 x float> %tmp1, i32 0
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%tmp3 = extractelement <2 x float> %tmp1, i32 1
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%tmp4 = fmul float %tmp3, 10.0
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%tmp5 = fadd float %tmp4, %tmp2
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store volatile float %tmp5, float addrspace(1)* undef
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ret void
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}
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; There should be exact one folding on the same operand.
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; CHECK-LABEL: {{^}}no_extra_fold_on_same_opnd
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @no_extra_fold_on_same_opnd() {
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entry:
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%s0 = load i32, i32 addrspace(5)* undef, align 4
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%s0.i64= zext i32 %s0 to i64
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br label %for.body.i.i
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for.body.i.i:
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%s1 = load i32, i32 addrspace(1)* undef, align 8
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%s1.i64 = sext i32 %s1 to i64
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%xor = xor i64 %s1.i64, %s0.i64
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%flag = icmp ult i64 %xor, 8
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br i1 %flag, label %if.then, label %if.else
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if.then:
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unreachable
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if.else:
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unreachable
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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