1e926a9f9c
Summary: This fixes some tests that did not specify -mcpu. Doing that disables all subtarget features, which gives behavior that (a) does not necessarily correspond to any actual target, and (b) can change as we add new subtarget features. Also added gfx1010 to memtime test. Differential Revision: https://reviews.llvm.org/D74594 Change-Id: I8c0fe4fa03e9a93ef8bb722cd42d22e064526309
288 lines
10 KiB
LLVM
288 lines
10 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-FLUSH -check-prefix=GCN %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-DENORM -check-prefix=GCN %s
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; GCN-LABEL: {{^}}mac_vvv:
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; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}
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; GCN: buffer_load_dword [[B:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4
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; GCN: buffer_load_dword [[C:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
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; GCN: v_mac_f32_e32 [[C]], [[A]], [[B]]
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; GCN: buffer_store_dword [[C]]
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define amdgpu_kernel void @mac_vvv(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load volatile float, float addrspace(1)* %in
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%b = load volatile float, float addrspace(1)* %b_ptr
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%c = load volatile float, float addrspace(1)* %c_ptr
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%tmp0 = fmul float %a, %b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad_inline_sgpr_inline:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]}}, s{{[0-9]+}}, 0.5, 0.5
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define amdgpu_kernel void @mad_inline_sgpr_inline(float addrspace(1)* %out, float %in) #0 {
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entry:
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%tmp0 = fmul float 0.5, %in
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%tmp1 = fadd float %tmp0, 0.5
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad_vvs:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @mad_vvs(float addrspace(1)* %out, float addrspace(1)* %in, float %c) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%tmp0 = fmul float %a, %b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mac_ssv:
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; GCN: v_mac_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @mac_ssv(float addrspace(1)* %out, float addrspace(1)* %in, float %a) #0 {
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entry:
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%c = load float, float addrspace(1)* %in
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%tmp0 = fmul float %a, %a
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mac_mad_same_add:
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; GCN: v_mad_f32 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, [[ADD:v[0-9]+]]
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; GCN: v_mac_f32_e32 [[ADD]], v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @mac_mad_same_add(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%d_ptr = getelementptr float, float addrspace(1)* %in, i32 3
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%e_ptr = getelementptr float, float addrspace(1)* %in, i32 4
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%a = load volatile float, float addrspace(1)* %in
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%b = load volatile float, float addrspace(1)* %b_ptr
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%c = load volatile float, float addrspace(1)* %c_ptr
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%d = load volatile float, float addrspace(1)* %d_ptr
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%e = load volatile float, float addrspace(1)* %e_ptr
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%tmp0 = fmul float %a, %b
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%tmp1 = fadd float %tmp0, %c
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%tmp2 = fmul float %d, %e
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%tmp3 = fadd float %tmp2, %c
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%out1 = getelementptr float, float addrspace(1)* %out, i32 1
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store float %tmp1, float addrspace(1)* %out
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store float %tmp3, float addrspace(1)* %out1
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ret void
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}
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; There is no advantage to using v_mac when one of the operands is negated
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; and v_mad accepts more operand types.
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; GCN-LABEL: {{^}}mad_neg_src0:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}
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define amdgpu_kernel void @mad_neg_src0(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_a = fsub float -0.0, %a
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%tmp0 = fmul float %neg_a, %b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}nsz_mad_sub0_src0:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}
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define amdgpu_kernel void @nsz_mad_sub0_src0(float addrspace(1)* %out, float addrspace(1)* %in) #1 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_a = fsub float 0.0, %a
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%tmp0 = fmul float %neg_a, %b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}safe_mad_sub0_src0:
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; GCN: v_sub_f32_e32 [[SUB0:v[0-9]+]], 0,
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; GCN: v_ma{{[cd]}}_f32{{[_e32]*}} v{{[0-9]+}}, [[SUB0]], v{{[0-9]+}}
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define amdgpu_kernel void @safe_mad_sub0_src0(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_a = fsub float 0.0, %a
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%tmp0 = fmul float %neg_a, %b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad_neg_src1:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}
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define amdgpu_kernel void @mad_neg_src1(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_b = fsub float -0.0, %b
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%tmp0 = fmul float %a, %neg_b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}nsz_mad_sub0_src1:
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; GCN-NOT: v_mac_f32
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; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}
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define amdgpu_kernel void @nsz_mad_sub0_src1(float addrspace(1)* %out, float addrspace(1)* %in) #1 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_b = fsub float 0.0, %b
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%tmp0 = fmul float %a, %neg_b
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%tmp1 = fadd float %tmp0, %c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad_neg_src2:
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; GCN-NOT: v_mac
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; GCN: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[-0-9]}}
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define amdgpu_kernel void @mad_neg_src2(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
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%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
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%a = load float, float addrspace(1)* %in
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%b = load float, float addrspace(1)* %b_ptr
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%c = load float, float addrspace(1)* %c_ptr
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%neg_c = fsub float -0.0, %c
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%tmp0 = fmul float %a, %b
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%tmp1 = fadd float %tmp0, %neg_c
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store float %tmp1, float addrspace(1)* %out
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ret void
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}
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; Without special casing the inline constant check for v_mac_f32's
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; src2, this fails to fold the 1.0 into a mad.
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; GCN-LABEL: {{^}}fold_inline_imm_into_mac_src2_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
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; GCN: v_add_f32_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]
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; GCN: v_mad_f32 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0
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define amdgpu_kernel void @fold_inline_imm_into_mac_src2_f32(float addrspace(1)* %out, float addrspace(1)* %a, float addrspace(1)* %b) #3 {
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bb:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds float, float addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds float, float addrspace(1)* %b, i64 %tid.ext
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%gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%tmp = load volatile float, float addrspace(1)* %gep.a
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%tmp1 = load volatile float, float addrspace(1)* %gep.b
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%tmp2 = fadd float %tmp, %tmp
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%tmp3 = fmul float %tmp2, 4.0
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%tmp4 = fsub float 1.0, %tmp3
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%tmp5 = fadd float %tmp4, %tmp1
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%tmp6 = fadd float %tmp1, %tmp1
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%tmp7 = fmul float %tmp6, %tmp
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%tmp8 = fsub float 1.0, %tmp7
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%tmp9 = fmul float %tmp8, 8.0
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%tmp10 = fadd float %tmp5, %tmp9
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store float %tmp10, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fold_inline_imm_into_mac_src2_f16:
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; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_ushort [[B:v[0-9]+]]
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; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[A]]
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; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[B]]
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; SI: v_add_f32_e32 [[TMP2:v[0-9]+]], [[CVT_A]], [[CVT_A]]
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; SI: v_mad_f32 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0
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; SI: v_mac_f32_e32 v{{[0-9]+}}, 0x41000000, v{{[0-9]+}}
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; VI-FLUSH: v_add_f16_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]
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; VI-FLUSH: v_mad_f16 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0
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define amdgpu_kernel void @fold_inline_imm_into_mac_src2_f16(half addrspace(1)* %out, half addrspace(1)* %a, half addrspace(1)* %b) #3 {
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bb:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.out = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
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%tmp = load volatile half, half addrspace(1)* %gep.a
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%tmp1 = load volatile half, half addrspace(1)* %gep.b
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%tmp2 = fadd half %tmp, %tmp
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%tmp3 = fmul half %tmp2, 4.0
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%tmp4 = fsub half 1.0, %tmp3
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%tmp5 = fadd half %tmp4, %tmp1
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%tmp6 = fadd half %tmp1, %tmp1
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%tmp7 = fmul half %tmp6, %tmp
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%tmp8 = fsub half 1.0, %tmp7
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%tmp9 = fmul half %tmp8, 8.0
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%tmp10 = fadd half %tmp5, %tmp9
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store half %tmp10, half addrspace(1)* %gep.out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" }
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attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind }
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