Kai Luo 4d20f495df

[PowerPC] Remove DAG matching in ADDIStocHA (#93905) ...

The MI is generated in `PPCDAGToDAGISel::Select` so the match pattern isn't used and can be removed.

2024-06-04 10:00:43 +08:00

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AArch64

[AArch64] Support preserve_none calling convention (#91046)

2024-06-03 18:42:08 -04:00

AMDGPU

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

ARC

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ARM

[ARM] Convert vector fdiv+fcvt fixed-point combine to fmul.

2024-06-03 09:31:36 +01:00

AVR

[MachineLICM] Hoist copies of constant physical register (#93285)

2024-05-29 14:10:01 +08:00

BPF

[BPF] report Invalid usage of the XADD return value" elegantly (#92742)

2024-05-21 01:57:56 +08:00

CSKY

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DirectX

[DirectX] Reapply Fix DXIL part header version encoding (#91956)

2024-05-13 18:50:16 -04:00

Generic

[VP][RISCV] Add vp.reduce.fmaximum/fminimum and its RISC-V codegen (#91782)

2024-05-10 16:01:47 -07:00

Hexagon

[Hexagon] Implement @llvm.readsteadycounter() (#93247)

2024-05-26 16:26:10 -05:00

Inputs

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Lanai

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LoongArch

[LoongArch] Custom legalize i32 operations for LA64 to reduce signed extensions (#93811)

2024-06-03 13:23:35 +08:00

M68k

[M68k] Fix compilation pipeline check

2024-05-31 20:06:54 -04:00

Mips

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

MIR

[Instrumentation] Support verifying machine function (#90931)

2024-05-04 09:00:59 +08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] disable combine-mad test for newer ptxas (#93919)

2024-06-01 09:28:56 -07:00

PowerPC

[PowerPC] Remove DAG matching in ADDIStocHA (#93905)

2024-06-04 10:00:43 +08:00

RISCV

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

SPARC

[test] Fix check prefixes

2024-05-13 11:25:12 -07:00

SPIRV

[SPIR-V] Fix legalize info for G_BITREVERSE (#93699)

2024-06-03 14:59:09 +02:00

SystemZ

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

Thumb

[Thumb] Resolve FIXME: Transform "(and (shl x, c2), c1)" into "(shl (and x, c1>>c2), c2)" (#82120)

2024-05-26 14:58:32 -04:00

Thumb2

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

VE

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WebAssembly

[WebAssembly] Implement all f16x8 relation instructions. (#93751)

2024-05-30 09:02:17 -07:00

WinCFGuard

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WinEH

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X86

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

XCore

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Xtensa

[Xtensa] Implement base CallConvention. (#83280)

2024-04-24 00:00:59 +02:00