Syadus Sefat 4dbd16bb62

[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#167798) ...

This patch adds register bank legalization support for buffer load byte
and short operations in the AMDGPU GlobalISel pipeline.

2025-12-12 10:35:15 -06:00

..

AArch64

[AArch64][SVE] Fix -msve-vector-bits=256 fixed width vector crash (#171776)

2025-12-12 15:21:14 +00:00

AMDGPU

[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#167798)

2025-12-12 10:35:15 -06:00

ARC

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ARM

[SDAG] Remove most non-canonical libcall handing (#171288)

2025-12-10 11:45:26 +01:00

AVR

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BPF

Revert "[BPF] Allow libcalls behind a feature gate (#168442)" (#169733)

2025-12-01 11:19:39 -08:00

CSKY

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DirectX

[NFC] Add missing analysis to DirectX/llc-pipeline (#170714)

2025-12-04 18:56:23 +00:00

Generic

[LLVM] Mark reloc-none test unsupported on Hexagon (#171205)

2025-12-08 21:36:23 +00:00

Hexagon

[Hexagon] Add HVX patterns for vector arithmetic (#170704)

2025-12-11 16:44:01 -06:00

Inputs

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Lanai

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LoongArch

[LoongArch] Add support for the ud macro instruction (#171583)

2025-12-11 13:31:03 +08:00

M68k

[M68k] Emit MOV16ds for moves from CCR on 68000 (#171703)

2025-12-11 14:44:32 -08:00

Mips

[Mips] Support "$sp" named register (#171793)

2025-12-12 16:11:29 +08:00

MIR

[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)

2025-12-03 13:56:15 +05:30

MIR2Vec

[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction (#151944)

2025-12-03 13:56:15 +05:30

MLRegAlloc

[MLGO] Remove Extra Dev Mode Features (#167273)

2025-11-10 08:40:28 -08:00

MSP430

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NVPTX

[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)

2025-12-09 22:39:11 +05:30

PowerPC

[NFC][PowerPC] Optimize vector compares for not equal to non zero vectors (#171635)

2025-12-12 11:23:14 +05:30

RISCV

[RISCV][llvm] Support PSRA, PSRAI, PSRL, PSRLI codegen for P extension (#171460)

2025-12-11 15:58:27 +08:00

SPARC

[SPARC][NFC] Update optcompare test that always returns false (#170025)

2025-12-05 20:35:03 +07:00

SPIRV

[HLSL] Implement ddx and ddy HLSL intrinsics (#168887)

2025-12-11 10:04:35 -08:00

SystemZ

[SDAG] Remove most non-canonical libcall handing (#171288)

2025-12-10 11:45:26 +01:00

Thumb

[DAG] Fold mul 0 -> 0 when expanding mul into parts. (#168780)

2025-12-05 07:58:28 +00:00

Thumb2

[DAG] Generate UMULH/SMULH with wider vector types (#170283)

2025-12-08 19:35:32 +00:00

VE

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WebAssembly

Revert "[WebAssembly] Implement addrspacecast to funcref" (#170785)

2025-12-04 17:24:14 -08:00

WinCFGuard

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WinEH

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X86

[X86] combineHorizOpWithShuffle - ensure we handle undef elements from widened shuffle (#172014)

2025-12-12 15:06:37 +00:00

XCore

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Xtensa

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