b5efec4b27
With D134950, targets get notified when a virtual register is created and/or cloned. Targets can do the needful with the delegate callback. AMDGPU propagates the virtual register flags maintained in the target file itself. They are useful to identify a certain type of machine operands while inserting spill stores and reloads. Since RegAllocFast spills the physical register itself, there is no way its virtual register can be mapped back to retrieve the flags. It can be solved by passing the virtual register as an additional argument. This argument has no use when the spill interfaces are called during the greedy allocator or even the PrologEpilogInserter and can pass a null register in such cases. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138656
124 lines
4.3 KiB
C++
124 lines
4.3 KiB
C++
//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AVR implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AVR_INSTR_INFO_H
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#define LLVM_AVR_INSTR_INFO_H
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "AVRRegisterInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "AVRGenInstrInfo.inc"
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#undef GET_INSTRINFO_HEADER
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namespace llvm {
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namespace AVRCC {
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/// AVR specific condition codes.
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/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
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/// They must be kept in synch.
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enum CondCodes {
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COND_EQ, //!< Equal
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COND_NE, //!< Not equal
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COND_GE, //!< Greater than or equal
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COND_LT, //!< Less than
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COND_SH, //!< Unsigned same or higher
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COND_LO, //!< Unsigned lower
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COND_MI, //!< Minus
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COND_PL, //!< Plus
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COND_INVALID
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};
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} // end of namespace AVRCC
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namespace AVRII {
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/// Specifies a target operand flag.
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enum TOF {
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MO_NO_FLAG,
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/// On a symbol operand, this represents the lo part.
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MO_LO = (1 << 1),
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/// On a symbol operand, this represents the hi part.
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MO_HI = (1 << 2),
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/// On a symbol operand, this represents it has to be negated.
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MO_NEG = (1 << 3)
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};
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} // end of namespace AVRII
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/// Utilities related to the AVR instruction set.
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class AVRInstrInfo : public AVRGenInstrInfo {
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public:
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explicit AVRInstrInfo();
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const AVRRegisterInfo &getRegisterInfo() const { return RI; }
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const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
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AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
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AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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void insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &NewDestBB,
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MachineBasicBlock &RestoreBB, const DebugLoc &DL,
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int64_t BrOffset, RegScavenger *RS) const override;
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private:
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const AVRRegisterInfo RI;
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};
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} // end namespace llvm
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#endif // LLVM_AVR_INSTR_INFO_H
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