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llvm-project/llvm/lib/Target/RISCV
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Michael Collison 764c1b7a4d [RISCV] Scheduler description for Bullet 
Add the pipeline model for the RISC-V Bullet micro architecture.

Co-authored-by: Evandro Menezes <evandro.menezes@sifive.com>
2020-09-25 18:36:53 -05:00
..
AsmParser
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
Disassembler
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
MCTargetDesc
[RISCV] Enable MCCodeEmitter instruction predicate verifier
2020-08-20 18:36:54 +01:00
TargetInfo
…
Utils
[RISCV] Support Shadow Call Stack
2020-09-17 16:02:35 -07:00
CMakeLists.txt
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
LLVMBuild.txt
…
RISCV.h
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
RISCV.td
[RISCV] Scheduler description for Bullet
2020-09-25 18:36:53 -05:00
RISCVAsmPrinter.cpp
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[RISCV] Support Shadow Call Stack
2020-09-17 16:02:35 -07:00
RISCVFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVInstrFormats.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
2020-09-21 10:21:11 +01:00
RISCVInstrInfo.h
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
2020-09-21 10:21:11 +01:00
RISCVInstrInfo.td
[RISCV] Do not mandate scheduling for CSR instructions
2020-09-21 18:24:53 -05:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVInstrInfoC.td
[RISC-V] Mark C_MV as a move instruction
2020-08-27 10:32:23 +01:00
RISCVInstrInfoD.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoF.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVISelDAGToDAG.h
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCVISelLowering.cpp
[RISCV] eliminate the repetition declare of SDLoc DL
2020-08-03 10:24:30 +08:00
RISCVISelLowering.h
[RISCV] Optimize multiplication by constant
2020-07-07 18:50:24 -07:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
2020-09-03 20:01:23 +08:00
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
RISCV: Don't store function in RISCVMachineFunctionInfo
2020-06-30 16:08:51 -04:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVSchedBullet.td
[RISCV] Scheduler description for Bullet
2020-09-25 18:36:53 -05:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[X86][MC][Target] Initial backend support a tune CPU to support -mtune
2020-08-14 15:31:50 -07:00
RISCVSubtarget.h
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.
2020-09-09 14:31:12 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00