llvm-project

History

[DAG] computeKnownBits - abds(x, y) will be zero in the upper bits if x and y are sign-extended (#94448 )

As reported on #94442 - if x and y have more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Sibling PR to #94382

Alive2: https://alive2.llvm.org/ce/z/7_z2Vc

Fixes #94442

2024-06-05 11:57:55 +01:00

CMakeLists.txt

…

DAGCombiner.cpp

[DAGCombine] Fix type mismatch in (shl X, cttz(Y)) -> (mul (Y & -Y), X) (#94008 )

2024-06-01 19:04:55 +08:00

FastISel.cpp

LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2024-04-25 17:50:59 -07:00

FunctionLoweringInfo.cpp

[CodeGen][SDAG] Track returntwice in lowering info (#92640 )

2024-05-19 16:39:19 +02:00

InstrEmitter.cpp

[ConstraintFP] Model rounding control registers for inline asm (#92846 )

2024-05-23 22:50:39 +08:00

InstrEmitter.h

…

LegalizeDAG.cpp

[SelectionDAG] Add an ISD::CLEAR_CACHE node to lower llvm.clear_cache (#93795 )

2024-05-30 14:55:32 +02:00

LegalizeFloatTypes.cpp

DAG: Handle fminnum_ieee/fmaxnum_ieee in basic legalization

2024-05-28 20:31:17 +02:00

LegalizeIntegerTypes.cpp

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799 )

2024-05-28 12:49:42 -07:00

LegalizeTypes.cpp

[SelectionDAG] Adjust placement of blank lines in debug output. NFC (#70969 )

2023-11-02 09:35:04 -07:00

LegalizeTypes.h

[ValueTypes] Remove MVT::MAX_ALLOWED_VALUETYPE. NFC (#93654 )

2024-05-29 11:47:21 -07:00

LegalizeTypesGeneric.cpp

[llvm][TypeSize] Fix addition/subtraction in TypeSize. (#72979 )

2023-11-22 08:52:53 +00:00

LegalizeVectorOps.cpp

[LegalizeVectorOps][X86] Add ISD::ABDS/ABSDU to the list of opcodes handled by LegalizeVectorOps. (#92332 )

2024-05-15 21:46:31 -07:00

LegalizeVectorTypes.cpp

DAG: Handle vector splitting for fminnum_ieee/fmaxnum_ieee

2024-05-28 22:58:24 +02:00

MatchContext.h

[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. (#82370 )

2024-02-23 14:17:15 +08:00

ResourcePriorityQueue.cpp

…

ScheduleDAGFast.cpp

[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible (#76708 )

2024-01-02 13:14:28 +00:00

ScheduleDAGRRList.cpp

[llvm] Move CodeGenTypes library to its own directory (#79444 )

2024-01-25 12:01:31 -05:00

ScheduleDAGSDNodes.cpp

[IR] Memory Model Relaxation Annotations (#78569 )

2024-04-24 08:52:25 +02:00

ScheduleDAGSDNodes.h

[llvm] Move CodeGenTypes library to its own directory (#79444 )

2024-01-25 12:01:31 -05:00

ScheduleDAGVLIW.cpp

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295 )

2023-09-14 14:10:14 -07:00

SDNodeDbgValue.h

…

SelectionDAG.cpp

[DAG] computeKnownBits - abds(x, y) will be zero in the upper bits if x and y are sign-extended (#94448 )

2024-06-05 11:57:55 +01:00

SelectionDAGAddressAnalysis.cpp

[CodeGen] Update for scalable MemoryType in MMO (#70452 )

2024-03-23 12:56:25 +00:00

SelectionDAGBuilder.cpp

[IR] Remove support for icmp and fcmp constant expressions (#93038 )

2024-06-04 08:31:03 +02:00

SelectionDAGBuilder.h

[IR] Remove support for icmp and fcmp constant expressions (#93038 )

2024-06-04 08:31:03 +02:00

SelectionDAGDumper.cpp

[SelectionDAG] Add an ISD::CLEAR_CACHE node to lower llvm.clear_cache (#93795 )

2024-05-30 14:55:32 +02:00

SelectionDAGISel.cpp

[CodeGen] Fix compiler conditional combination (#94297 )

2024-06-04 09:16:00 +08:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[StatepointLowering] Use Constant instead of TargetConstant for undef value (#81635 )

2024-02-13 21:58:01 +03:00

StatepointLowering.h

…

TargetLowering.cpp

[DAG] Replace getValid*ShiftAmountConstant helpers with getValid*ShiftAmount helpers to support KnownBits analysis (#93182 )

2024-06-01 16:48:26 +01:00