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llvm-project/llvm/test/CodeGen/RISCV
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Craig Topper d9320e22d4 [RISCV][GlobalISel] Select register banks for GPR ALU instructions 
This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.

Co-authored-by: Lewis Revill <lewis.revill@embecosm.com>

Reviewed By: nitinjohnraj

Differential Revision: https://reviews.llvm.org/D76051
2023-08-22 12:31:20 -07:00
..
GlobalISel
[RISCV][GlobalISel] Select register banks for GPR ALU instructions
2023-08-22 12:31:20 -07:00
intrinsics
…
rvv
[RISCV] Match strided loads with reversed indexing sequences
2023-08-22 07:59:49 -07:00
add-before-shl.ll
[RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.
2023-06-22 09:22:58 -07:00
add-imm.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
addc-adde-sube-subc.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
addcarry.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
addimm-mulimm.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
addrspacecast.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
aext-to-sext.ll
[InstCombine][CGP] Move swapMayExposeCSEOpportunities() fold
2023-06-15 14:17:58 +02:00
align-loops.ll
[RISCV] Add tune features of preferred function/loop align
2023-08-15 12:04:12 +08:00
align.ll
[RISCV] Add tune features of preferred function/loop align
2023-08-15 12:04:12 +08:00
alloca.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu8.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu16.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu32.ll
…
alu64.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
analyze-branch.ll
…
and-add-lsr.ll
[DAGCombine] Canonicalize operands for visitANDLike
2023-07-24 16:52:04 +08:00
and.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
arith-with-overflow.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
atomic-cmpxchg-branch-on-result.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg-flag.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg.ll
[RISC-V] Add proposed mapping for Ztso
2023-08-10 15:59:06 +01:00
atomic-fence.ll
[RISCV] Implement a proposed mapping for Ztso
2023-02-09 12:00:05 -08:00
atomic-load-store.ll
[RISC-V] Add proposed mapping for Ztso
2023-08-10 15:59:06 +01:00
atomic-rmw.ll
[RISC-V] Add proposed mapping for Ztso
2023-08-10 15:59:06 +01:00
atomic-signext.ll
[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
2023-07-25 09:03:45 -07:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Generalize combineAddOfBooleanXor to support any boolean not just setcc.
2023-07-25 09:04:49 -07:00
attributes.ll
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
bf16-promote.ll
[RISCV] Expand load extension / truncate store for bf16
2023-08-01 11:10:41 +08:00
bfloat-arith.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-br-fcmp.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-convert.ll
[LegalizeTypes][RISCV] Correct FP_TO_{S,U}INT expansion when bf16 isn't a legal type
2023-08-09 11:01:28 +01:00
bfloat-fcmp.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-frem.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-imm.ll
[RISCV] Add bf16 to isFPImmLegal.
2023-08-03 08:27:38 -07:00
bfloat-isnan.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-mem.ll
[RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps
2023-08-03 07:06:57 +01:00
bfloat-select-fcmp.ll
[RISCV] Implement support for bf16 select when zfbfmin is enabled
2023-08-02 20:04:30 +01:00
bfloat-select-icmp.ll
[RISCV] Add bf16 to isFPImmLegal.
2023-08-03 08:27:38 -07:00
bfloat.ll
Recommit "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"
2023-06-23 17:23:12 -07:00
bitextract-mac.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
bitreverse-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
bittest.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
blockaddress.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
branch_zero.ll
[RISCV] Omit SRA in case of setlt or setge with zero constant
2022-12-21 14:19:49 +03:00
branch-on-zero.ll
[RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare
2023-02-28 14:43:40 +08:00
branch-relaxation.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
branch.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
bswap-bitreverse.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
bswap-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
byval.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
callee-saved-fpr32s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-fpr64s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-gprs.ll
[RISCV] Use max pushed register to get pushed register number.
2023-08-03 14:49:15 +08:00
calling-conv-half.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
calling-conv-ilp32-ilp32f-common.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
calling-conv-lp64-lp64f-lp64d-common.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-vector-on-stack.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
calls.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
cm_mvas_mvsa.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
cmp-bool.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
codemodel-lowering.ll
[RISCV] Lower extern_weak symbols using the GOT for the medany model
2023-05-31 18:48:21 +01:00
compress-double.ll
[RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines.
2023-06-27 09:44:51 -07:00
compress-float.ll
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
compress-inline-asm.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
compress-opt-branch.ll
[RISCV] Optimization for using compressed beqz and bnez PR#56391
2022-10-06 09:33:32 -07:00
compress-opt-select.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
compress.ll
[RISCV] Add integer scalar instructions to isAssociativeAndCommutative
2022-12-29 11:43:40 +00:00
condbinops.ll
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
2023-08-01 11:27:10 -04:00
condops.ll
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
copy-frameindex.mir
llvm-reduce: Don't assert on functions which don't track liveness
2022-06-07 10:00:25 -04:00
copyprop.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
copysign-casts.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
ctlz-cttz-ctpop.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
ctz_zero_return_test.ll
[RISCV] Add DAG combine for CTTZ/CTLZ in the case of input 0
2023-07-19 16:22:04 +02:00
disable-tail-calls.ll
…
disjoint.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
div_minsize.ll
[RISCV]Enable isIntDivCheap when attribute is minsize
2022-07-27 18:22:51 +08:00
div-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
div-pow2.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
div.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
double_reduct.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
double-arith-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-arith.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-br-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-calling-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
double-convert.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-frem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-imm.ll
[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
2023-08-02 20:16:50 -07:00
double-intrinsics-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-isnan.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
double-mem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-previous-failure.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv-sat.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
double-stack-spill-restore.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
dso_local_equivalent.ll
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
dwarf-eh.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
early-clobber-tied-def-subreg-liveness.ll
InlineSpiller: Consider copy bundles when looking for snippet copies
2023-06-20 12:26:27 -04:00
eh-dwarf-cfa.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
elf-preemption.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
emutls.ll
[RISCV] Support emulated TLS
2023-03-29 20:55:51 +01:00
exception-pointer-register.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fastcc-float.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
fastcc-int.ll
…
fastcc-without-f-reg.ll
[RISCV] Use the stack for MVT::f16 for fastcc when there are no other registers available
2023-07-18 19:49:17 -07:00
fixups-diff.ll
[RISCV] Allow delayed decision for ADD/SUB relocations
2023-07-21 08:37:58 -07:00
fli-licm.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
float-arith-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-arith.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bit-preserving-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-br-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-frem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-imm.ll
[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
2023-08-02 20:16:50 -07:00
float-intrinsics-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics.ll
[RISCV] Update computeKnownBitsForTargetNode for FPCLASS.
2023-06-29 14:13:01 +08:00
float-isnan.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
float-mem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv-sat.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
float-select-verify.ll
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
2023-02-03 22:42:08 -08:00
float-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
flt-rounds.ll
[Intrinsic] Rename flt.rounds intrinsic to get.rounding
2022-12-19 15:22:39 +08:00
fmax-fmin.ll
[SDAG] avoid libcalls to fmin/fmax for soft-float targets
2022-03-30 11:22:03 -04:00
fold-addi-loadstore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fold-binop-into-select.ll
Reapply [RISCV] Fold binary op into select if profitable.
2023-07-14 15:30:54 -04:00
forced-atomics.ll
[RISCV] Strengthen atomic ordering for sequentially consistent stores
2023-06-22 15:42:17 +00:00
fp16-promote.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
fp128.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fpclamptosat.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
fpenv.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
frame-info.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
frame.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
frameaddr-returnaddr.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
frm-dependency.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
get-register-reserve.ll
…
get-setcc-result-type.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
ghccc-nest.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
ghccc-rv32.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
ghccc-rv64.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
ghccc-without-f-reg.ll
[RISCV] Support register allocation for GHC when f/d is not specified in the architecture
2023-07-23 22:40:10 -07:00
global-merge-offset.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
global-merge.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
half-arith-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-arith.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-br-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-convert-strict.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-convert.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-fcmp-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-frem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-imm.ll
[RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC
2023-08-02 20:16:50 -07:00
half-intrinsics.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-isnan.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
half-mem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-round-conv-sat.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
half-round-conv.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
half-select-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
half-zfa-fli.ll
[RISCV] Pre-commit tests for D145897. NFC
2023-03-14 13:11:11 -07:00
half-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
hoist-global-addr-base.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
hwasan-check-memaccess.ll
[RISC-V][HWASAN] Don't explicitly load GOT entry to call hwasan mismatch routine
2023-01-09 16:46:28 +03:00
i32-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
i64-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
iabs.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
imm-cse.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
imm.ll
[RISCV] Don't use (ADD (SLLI C, 32), C) to materialize constants when optimizing for size.
2023-06-12 09:52:35 -07:00
indirectbr.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
init-array.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-mem-constraint.ll
[RISCV] Support global address as inline asm memory operand of m
2023-08-21 18:59:52 +08:00
inline-asm-S-constraint.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
inline-asm-zfh-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm.ll
[RISCV][NFC] Move tests of inline asm memory constraints to separate file
2023-08-21 18:59:52 +08:00
inline-option-directive.ll
[RISCV] Support '.option arch' directive
2023-05-26 18:39:41 +08:00
interrupt-attr-args-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr-callee.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
interrupt-attr-ret-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
isel-optnone.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
jumptable.ll
Revert "[CodeGen][ShrinkWrap] Split restore point"
2023-04-13 10:52:28 +05:30
kcfi-isel-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-patchable-function-prefix.ll
MachineFunction: -fsanitize={function,kcfi}: ensure 4-byte alignment
2023-06-30 09:13:19 -07:00
kcfi.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
lack-of-signed-truncation-check.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
large-stack.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
legalize-fneg.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
libcall-tail-calls.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
live-sp.mir
…
llvm.frexp.ll
[RISCV][test] Add RV32I and RV64I RUN lines to llvm.frexp.ll
2023-07-06 13:36:03 +01:00
local-stack-slot-allocation.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions
2023-01-24 11:42:37 -08:00
lsr-legaladdimm.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
machine-combiner-mir.ll
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
2022-11-17 13:24:04 +03:00
machine-combiner-strategies.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
machine-combiner.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-combiner.mir
[RISCV] Clear kill flags when forming FMA instructions in MachineCombiner.
2023-07-12 08:03:45 -07:00
machine-cp.mir
[MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow.
2022-06-17 21:40:08 -07:00
machine-cse.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-outliner-and-machine-copy-propagation.ll
[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
2023-03-14 17:55:11 +00:00
machine-outliner-cfi.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-patchable.ll
…
machine-outliner-position.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-throw.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
machinelicm-address-pseudos.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel-lo operand.
2022-08-24 21:47:46 +08:00
machineoutliner.mir
[MachineOutliner] Add IsOutlined to MachineFunction
2023-04-10 10:57:29 +08:00
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
make-compressible-for-store-address.mir
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
make-compressible-rv64.mir
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
make-compressible.mir
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mem64.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
mem.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
memcpy-inline.ll
[RISCV] Add memcpy lowering test coverage with and without V
2023-07-24 12:25:09 -07:00
memcpy.ll
[RISCV] Add memcpy lowering test coverage with and without V
2023-07-24 12:25:09 -07:00
memset-inline.ll
[RISCV] Set Fast flag for unaligned memory accesses
2023-07-24 10:58:57 +01:00
min-max.ll
[SelectionDAG] Improve expansion of wide min/max
2023-06-26 10:45:41 -07:00
mir-target-flags.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
miss-sp-restore-eh.ll
[RISCV] Fix missing stack pointer recover
2022-06-09 23:38:50 +08:00
module-target-abi2.ll
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
2022-03-24 00:48:52 +08:00
module-target-abi3.ll
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
2022-08-26 14:39:39 +08:00
module-target-abi.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mul.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
musttail-call.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
narrow-shl-cst.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
neg-abs.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
nest-register.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
nomerge.ll
[CodeGen] Fix nomerge attribute not working in tail calls.
2023-05-10 14:25:11 -04:00
nontemporal-scalable.ll
[RISCV] Remove experimental for zihintntl
2023-08-10 17:04:49 +08:00
nontemporal.ll
[RISCV] Remove experimental for zihintntl
2023-08-10 17:04:49 +08:00
O0-pipeline.ll
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
O3-pipeline.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
option-nopic.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
or-is-add.ll
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
2022-12-28 19:59:42 -08:00
out-of-reach-emergency-slot.mir
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
overflow-intrinsic-optimizations.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
overflow-intrinsics.ll
[RISCV] Add special case for i32 uaddo X, -1 on RV64.
2023-04-01 18:54:03 -07:00
patchable-function-entry.ll
[AsmPrinter] Fix placement of function entry comments
2023-04-18 15:01:36 -07:00
pic-models.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr40333.ll
…
pr51206.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
pr53662.mir
[RISCV] Don't getDebugLoc for the end node of MBB iterator
2022-04-30 16:00:20 +08:00
pr55201.ll
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
2022-04-30 11:02:30 -07:00
pr56110.ll
[DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.
2022-06-19 15:50:15 -07:00
pr56457.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
pr58025.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58286.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58511.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
pr63365.ll
[CodeGenPrepare][RISCV] Remove asserting VH references before erasing the dead GEP
2023-06-18 23:40:47 +08:00
pr63816.ll
[LegalizeDAG] Prevent LegalizeLoadOps from creating extloads that mix int and fp types.
2023-07-12 08:03:35 -07:00
pr64503.ll
[DAGCombiner] Fold trunc(undef) -> undef.
2023-08-14 13:02:24 -07:00
pr64645.ll
[RISCV] Fix assertion when passing f64 vectors via integer registers
2023-08-15 12:11:08 +08:00
pr64772.ll
[DAGCombiner][RISCV] Return SDValue(N, 0) instead of SDValue() after 2 calls to CombineTo in visitSTORE.
2023-08-17 15:13:36 -07:00
prefetch.ll
[RISCV] Remove experimental for zihintntl
2023-08-10 17:04:49 +08:00
push-pop-opt-crash.ll
[RISCV] Add bounds check before use on returned iterator.
2023-08-14 16:06:09 -07:00
push-pop-popret.ll
[RISCV] Fix the CFI offset for callee-saved registers stored by Zcmp push.
2023-08-02 13:03:21 +08:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
rem.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
remat.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
repeated-fp-divisors.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
reserved-reg-errors.ll
…
reserved-regs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
riscv-codegenprepare-asm.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
riscv-codegenprepare.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
riscv-func-target-feature.ll
[RISCV] Fix zihintntl test
2023-08-10 17:18:17 +08:00
rotl-rotr.ll
[DAG] SimplifyDemandedBits - call ComputeKnownBits for constant non-uniform ISD::SRL shift amounts
2023-07-21 14:52:57 +01:00
rv32-fuchsia.ll
[llvm] Prevent building for riscv32-unknown-fuchsia
2023-03-01 19:42:56 +00:00
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
rv32xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv32xtheadbb.ll
[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
2023-02-17 21:46:26 +01:00
rv32xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv32zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv32zbb-intrinsic.ll
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
2022-03-28 16:56:33 -07:00
rv32zbb-zbkb.ll
[RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant.
2022-12-29 15:10:36 -08:00
rv32zbb.ll
[SelectionDAG] Improve expansion of wide min/max
2023-06-26 10:45:41 -07:00
rv32zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv32zbkb.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
rv32zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbs.ll
[RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./
2022-12-29 17:04:52 -08:00
rv32zknd-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknd-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64-large-stack.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rv64d-double-convert-strict.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll
[RISCV] Set target-abi explicitly to reduce codegen results
2022-06-01 13:49:23 +08:00
rv64f-float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
rv64i-complex-float.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
rv64i-demanded-bits.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
rv64i-shift-sext.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv64xtheadbb.ll
[RISCV] Remove unused CHECK prefix from test. NFC
2023-07-30 22:15:54 -07:00
rv64xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv64zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv64zbb-intrinsic.ll
[RISCV] Remove support for the unratified Zbp extension.
2022-09-21 21:22:42 -07:00
rv64zbb-zbkb.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
rv64zbb.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
rv64zbc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbkb-intrinsic.ll
[RISCV] Support i32 brev8 intrinsic on RV64.
2023-07-06 17:24:53 -07:00
rv64zbkb.ll
[RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.
2023-06-06 13:30:33 -07:00
rv64zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbs.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rv64zfh-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfh-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfhmin-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zknd-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknd-zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade2.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv64zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rve.ll
[RISCV][MC] Add support for RV64E
2023-03-23 12:32:25 +00:00
sadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
sadd_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
saverestore-scs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
saverestore.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
sdata-limit-0.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-4.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-8.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-local-sym.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
select-and.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-bare.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-binop-identity.ll
[RISCV] Call combineSelectToBinOp before generic select expansion for Zicond.
2023-08-01 12:09:35 -07:00
select-cc.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
select-const.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-constant-xor.ll
[RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
2022-12-28 15:17:41 -08:00
select-optimize-multiple.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-optimize-multiple.mir
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-or.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select.ll
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
2023-08-01 11:27:10 -04:00
selectcc-to-shiftand.ll
[RISCV] Match neg (and x, 1) to two shifts to improve codesize
2022-12-19 14:17:26 -08:00
setcc-logic.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
sext-zext-trunc.ll
[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB
2023-03-24 09:45:43 +08:00
sextw-removal.ll
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
2023-08-01 11:27:10 -04:00
shadowcallstack.ll
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
shift-amount-mod.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shift-and.ll
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
2022-10-22 14:30:13 -07:00
shift-masked-shamt.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shifts.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shl-demanded.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
shlimm-addimm.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
short-foward-branch-opt.ll
[RISCV] Support the short-forward-branch predicated ops in RISCVSExtWRemoval.
2022-12-23 21:39:22 -08:00
shrinkwrap-jump-table.ll
[ShrinkWrap] Allow shrinkwrapping past memory accesses to jump tables
2023-05-11 11:33:18 -07:00
shrinkwrap.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
signbit-test.ll
[AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
2022-12-06 11:34:48 -05:00
signed-truncation-check.ll
[RISCV] Enable signed truncation check transforms for i8
2023-05-10 22:53:24 +08:00
sink-icmp.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
spill-fpr-scalar.ll
[RISCVInsertVSETVLI] Default to VL=1 for scalar extracts
2023-08-16 07:35:00 -07:00
split-offsets.ll
[RISCV] Pre-commit test case from PR62734. NFC
2023-05-16 16:07:23 -07:00
split-sp-adjust.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
split-store.ll
[RISCV] Implement isMultiStoresCheaperThanBitsMerge hook
2023-01-31 12:47:48 +00:00
split-udiv-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
split-urem-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
srem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
srem-seteq-illegal-types.ll
[RISCV] Reduce LMUL for vector extracts
2023-08-22 07:36:17 -07:00
srem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
stack-folding.ll
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
stack-inst-compress.mir
[RISCV] Compress stack insts by adjust offset.
2023-08-18 10:49:53 +08:00
stack-protector-target.ll
[RISCV] Clean up stack-protector-target test
2023-02-06 16:42:59 -08:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-realignment.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-slot-coloring.mir
[RISCV] Set how many bytes load from or store to stack slot
2023-03-10 10:14:59 +08:00
stack-slot-size.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-store-check.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
subtarget-features-std-ext.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
switch-width.ll
[riscv] Add a bunch of tests exploring switch lowering
2022-05-11 13:16:31 -07:00
tagged-globals.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
tail-calls.ll
[RISCV] Permit tail call to an externally-defined function with weak linkage
2023-02-03 09:38:46 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
tls-models.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
trunc-free.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
uadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
uadd_sat.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
umulo-128-legalisation-lowering.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
unaligned-load-store.ll
[RISCV] Set Fast flag for unaligned memory accesses
2023-07-24 10:58:57 +01:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
unroll-loop-cse.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
urem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
urem-seteq-illegal-types.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
urem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
vararg.ll
[RISCV] Enable alias analysis by default
2023-08-10 10:48:43 +08:00
vector-abi.ll
…
verify-instr.mir
…
vlenb.ll
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
2022-05-16 16:38:30 -07:00
vscale-demanded-bits.ll
SelectionDAG: Teach ComputeKnownBits about VSCALE
2023-05-26 10:48:49 -07:00
wide-mem.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
wide-scalar-shift-by-byte-multiple-legalization.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
wide-scalar-shift-legalization.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
xaluo.ll
[RISCV] Call combineSelectToBinOp before generic select expansion for Zicond.
2023-08-01 12:09:35 -07:00
xtheadfmemidx.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
xtheadmac.ll
[RISCV] xtheadmac: fix commutativity issue for the in/out register
2023-02-17 19:45:22 +01:00
xtheadmemidx.ll
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
2023-02-24 00:17:58 +01:00
xtheadmempair.ll
[RISCV] XTHeadMemPair: Fix invalid mempair combine for types other than i32/i64
2023-02-22 19:57:37 +01:00
zbb-cmp-combine.ll
[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns
2023-07-17 17:13:47 -07:00
zdinx-boundary-check.ll
[RISCV] Enable alias analysis by default
2023-08-10 10:48:43 +08:00
zext-with-load-is-free.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
zfbfmin.ll
[RISCV] Add codegen for Zfbfmin instructions
2023-07-24 10:37:58 +08:00
zfh-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zmmul.ll
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00