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llvm-project/llvm/test/CodeGen
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Tim Northover 5f65ee260d AArch64+GISel: legalize vector remainder operations.
2021-10-05 10:20:10 +01:00
..
AArch64
AArch64+GISel: legalize vector remainder operations.
2021-10-05 10:20:10 +01:00
AMDGPU
[AMDGPU] Pre-commit test for D111126 (NFC)
2021-10-05 18:13:54 +09:00
ARC
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
2021-09-10 13:04:08 -07:00
ARM
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
AVR
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BPF
BPF: make 32bit register spill with 64bit alignment
2021-09-20 21:00:25 -07:00
Generic
Moved the test to X86 as it's x86 specific.
2021-08-31 14:48:29 -04:00
Hexagon
[LiveIntervals] Repair subreg ranges in processTiedPairs
2021-09-28 08:10:16 +01:00
Inputs
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Lanai
[Lanai] implement wide immediate support
2021-09-10 10:54:43 +00:00
M68k
[M68k][test] Migrate the remaining fixup and relaxation tests
2021-09-04 16:27:13 -07:00
Mips
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
MIR
[Tests] Fix incorrect noalias metadata
2021-09-18 20:51:00 +02:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
Fix tests defaulting to incorrect triples on AIX
2021-09-27 11:30:45 -04:00
PowerPC
[PowerPC][NFC] Remove reg name option in int128 test
2021-10-04 15:31:25 +00:00
RISCV
[RISCV] Add riscv64 command line to hoist-global-addr-base.ll. NFC
2021-10-04 17:01:59 -07:00
SPARC
Fix tests defaulting to incorrect triples on AIX
2021-09-27 11:30:45 -04:00
SystemZ
[LiveIntervals] Repair subreg ranges in processTiedPairs
2021-09-28 08:10:16 +01:00
Thumb
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
Thumb2
[ARM] Add more MVE intrinsics to sink splats to
2021-09-30 14:41:23 +01:00
VE
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WebAssembly
[WebAssembly] Add prototype relaxed SIMD fma/fms instructions
2021-09-23 11:01:36 -07:00
WinCFGuard
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WinEH
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
X86
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
XCore
…