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Justin Fargnoli 9475f6af81
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116) 
Previous commit message: 

>Previous commit message: 
>
>> Original commit message:
>>
>>>When users explicitly specify a PTX version via -mattr=+ptxNN that's
insufficient for their target SM, we now emit a fatal error. Previously,
we silently upgraded the PTX version to the minimum required for the
target SM.
>>>
>>>When no SM or PTX version is specified, we now use PTX 3.2 (the
minimum for the default SM 3.0) instead of PTX 6.0.
>>
>>The following commits should fix the failures that arose when I
previously tried to land this commit:
>>
>>

>>9fc5fd0ad6
should address the llvm-nvptx*-nvidia-* build failures:
https://github.com/llvm/llvm-project/pull/174834#issuecomment-3742242651
>>
>>

>>600514a637
should address the MLIR failures
>
>The previous commit was reverted with
d23cb79ba4
because the
[mlir-nvidia](https://lab.llvm.org/buildbot/#/builders/138/builds/24797)
and
[mlir-nvidia-gcc7](https://lab.llvm.org/buildbot/#/builders/116/builds/23929)
Buildbots were failing.
>
>Those tests failed because MLIR's default SM was 5.0, which caused
NVPTX
to target PTX ISA v4.0, which did not support the intrinsics used in the
failing tests.
>

>243f011577
should address this by bumping MLIR's default SM to 7.5. Now, using
MLIR's new default SM, NVPTX
targets the PTX ISA v6.3, which supports the intrinsics used in the
failing tests.

---

The previous commit was reverted with
e9b578a4d77025e18318efedd0f3f3764338d859
[because](https://github.com/llvm/llvm-project/pull/179304#issuecomment-3856301333)
the clang driver set the default PTX ISA version to v4.2 when no CUDA
installation is found. However, given our patch, we should not set a
default; instead, let the LLVM backend select the appropriate PTX ISA
version for the target SM.
2026-02-10 18:11:54 +00:00
..
access-non-generic.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
activemask.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
add-sub-128bit.ll
[NVPTX] Cleanup ISel for selp.* (#135065)
2025-04-09 14:21:12 -07:00
addr-mode.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
addrspacecast-cse.ll
[SDAG] Fix CSE for ADDRSPACECAST nodes (#122912)
2025-01-20 09:09:22 -08:00
addrspacecast-folding.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
addrspacecast-gvar.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
addrspacecast-ptx64.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
addrspacecast.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
aggr-param.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
aggregate-return.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
alias-errors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
alias.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
and-or-setcc.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
annotations.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
anonymous-fn-param.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
APIntLoadStore.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntSextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
APIntZextParam.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
applypriority.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
arg-lowering.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
arithmetic-fp-sm20.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
arithmetic-int.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
async-copy.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
atomic-lower-local.ll
…
atomicrmw-expand.err.ll
[NVPTX] add support for 128-bit atomics (#154852)
2025-08-28 10:41:46 -07:00
atomicrmw-sm60.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw-sm70.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw-sm90.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw.py
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomics-b128.ll
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
atomics-sm60.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomics-with-scope.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
atomics.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
b52037.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
barrier.ll
[NVPTX] Add missing type suffixes for barrier.cta.red (#172945)
2025-12-19 05:53:49 -08:00
bf16-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bf16.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
bf16x2-instructions-approx.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
bf16x2-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bfe.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
blocksareclusters-kernel-attr.ll
[NVPTX] Add support for "blocksareclusters" kernel attr (#152265)
2025-08-20 11:09:39 +05:30
bmsk.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
boolean-patterns.ll
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
branch-fold.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
branch-fold.mir
[NVPTX] miscellaneous minor cleanup (NFC) (#152329)
2025-08-12 18:15:01 -07:00
brkpt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bswap.ll
[NVPTX] Use PRMT instruction to lower i16 bswap (#168968)
2025-11-24 16:11:05 -08:00
bug17709.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bug21465.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
bug22246.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bug22322.ll
[DAGCombiner] Remove most NoSignedZerosFPMath uses (#161180)
2025-09-30 11:44:34 +08:00
bug26185-2.ll
Partial revert "[NVPTX] Enhance mul.wide and mad.wide peepholes #150477" (#155024)
2025-08-25 22:11:18 +00:00
bug26185.ll
[NVPTX] Cleanup ld/st lowering (#143936)
2025-06-17 09:00:18 -07:00
bug41651.ll
…
bug52623.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
bypass-div.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
byval-arg-vectorize.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
byval-const-global.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
call_bitcast_byval.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
call-with-alloca-buffer.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
callchain.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
calling-conv.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
calls-with-phi.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
chain-different-as.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
cluster-dim.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
clusterlaunchcontrol-multicast.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
clusterlaunchcontrol.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cmpxchg-sm60.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-sm70.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-sm90.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-unsupported-syncscope.err.ll
[test] Avoid writing test output to readonly dir (#166404)
2025-11-04 17:54:43 +00:00
cmpxchg.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cmpxchg.py
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
combine-mad.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
combine-min-max.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
combine-mul-wide-type.ll
[NVPTX] Use correct mul.wide operand type when matching on shl in combineMulWide (#168986)
2026-01-08 09:27:40 -08:00
combine-wide.ll
[NVPTX] Reland mad.wide combine under (default off) CLI option (#160214)
2025-09-25 10:23:56 -07:00
common-linkage.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
compare-int.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
compute-ptx-value-vts.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
constant-vectors.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
convergent-mir-call.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
convert-call-to-indirect.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
convert-fp-i8.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
convert-fp.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
convert-int-sm20.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
convert-sm80-sf.ll
[clang][NVPTX] Add remaining float to fp16 conversions (#167641)
2025-11-19 13:03:33 +05:30
convert-sm80.ll
[clang][NVPTX] Add remaining float to fp16 conversions (#167641)
2025-11-19 13:03:33 +05:30
convert-sm89.ll
[clang][NVPTX] Fix SM requirement of f32-tf32 rna satfinite conversion (#167836)
2025-11-18 09:29:10 +05:30
convert-sm90.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
convert-sm100.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
convert-sm100a.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
convert-sm103a.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
copysign.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
cp-async-bulk-ptx86.ll
[NVPTX] Add TMA non-tensor variant of g2s-cta intrinsic (#167508)
2025-11-13 15:33:46 +05:30
cp-async-bulk-s2g-sm100.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-g2s-1cta.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-2cta.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-cta-sm90.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-g2s-cta-sm100.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-g2s-cta-sm100a.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-g2s-gather4.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-im2colw128.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-im2colw.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-invalid.ll
[NVPTX] Add cta_group support to TMA G2S intrinsics (#143178)
2025-06-12 15:20:39 +05:30
cp-async-bulk-tensor-g2s.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-prefetch-sm100a.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-prefetch.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-reduce.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-s2g-scatter4.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk-tensor-s2g.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cp-async-bulk.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
cse-mov-sym.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
ctlz.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
ctpop.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
cttz.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dag-cse.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
default-sm.ll
[NVPTX] Update the default SM to 7.5 (#176021)
2026-01-22 18:26:55 +00:00
demote-vars.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
disable-opt.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
discard.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
disjoint-or-addr.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
distributed-shared-cluster.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
div-ri.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
div.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
divrem-combine.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
dot-product.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
dynamic_stackalloc.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
dynamic-stackalloc-regression.ll
[NVPTX] Fixup under-aligned dynamic alloca lowering (#139628)
2025-05-13 09:56:41 -07:00
elect.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
empty-type.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
envreg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
extern-shared-valid-name.ll
[NVPTX] fix illegal name for .extern .shared global variables (#173018)
2026-01-22 21:28:07 +01:00
extloadv.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
extractelement.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
f16-abs.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
f16-add-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16-ex2.ll
[NVPTX] Add ex2.approx bf16 support and cleanup intrinsic definition (#165446)
2025-11-01 17:51:17 +00:00
f16-instructions.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
f16-mul-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16-sub-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16x2-instructions.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
f32-ex2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
f32-lg2.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
f32x2-convert-i32x2.ll
[NVPTX] expand trunc/ext on v2i32 (#161715)
2025-10-02 13:13:36 -07:00
f32x2-instructions.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fabs-intrinsics.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fast-math.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fcos-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
fence-cluster.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
fence-nocluster.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
fence-proxy-sm90-ptx86.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-sm90.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-tensormap-invalid.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-tensormap.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fence-proxy.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence.py
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
fexp2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
filetype-null.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
flo.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
flog2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
fma-assoc.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fma-disable.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fma-oob.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
fma-relu-contract.ll
[NVPTX] Remove NoSignedZerosFPMath uses (#180086)
2026-02-06 13:32:12 +08:00
fma-relu-fma-intrinsic.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
fma-relu-instruction-flag.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
fma.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
fmax3.ll
[NVPTX] Add 3-operand fmin/fmax DAGCombines (#159729)
2025-09-22 14:01:14 +01:00
fminimum-fmaximum.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fns.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fold-movs.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
forward-ld-param.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
fp128-storage-type.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
fp-arith-sat.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
fp-contract-f32x2.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
fp-contract.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
fp-fold-sub.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
fp-literals.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
frameindex-lifetime.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
frem.ll
[NVPTX] Remove UnsafeFPMath uses (#151479)
2025-08-14 08:42:29 +08:00
fsin-no-fast-math.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
function-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
funnel-shift-clamp.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
generic-to-nvvm-ir.ll
…
generic-to-nvvm.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
global-addrspace.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
global-ctor-empty.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-incomplete-init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
global-ordering.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
global-variable-big.ll
[NVPTX] Basic support for fp128 as a storage type (#136006)
2025-04-17 13:19:48 -07:00
global-visibility.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_init.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
globals_lowering.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
griddepcontrol.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
gvar-init.ll
[NVPTX][test] Use 'not' to switch an XFAIL test to PASS (#130839)
2025-03-12 09:20:48 -07:00
half.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i1-array-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-ext-load.ll
[NVPTX] Cleanup ld/st lowering (#143936)
2025-06-17 09:00:18 -07:00
i1-global.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-icmp.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
i1-int-to-fp.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
i1-load-lower.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
i1-param.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
i1-select.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
i8-param.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i8x2-instructions.ll
Reland "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines" (#155063)
2025-08-25 09:15:44 -07:00
i8x4-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
i16x2-instructions.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
i32x2-instructions.ll
[NVPTX] fix truncating/extending loads/stores for v2i32 (#163838)
2025-10-16 13:25:34 -07:00
i128-array.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
i128-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128-ld-st.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
i128-param.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
i128-retval.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
i128-struct.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
i128.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
idioms.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
imad.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
indirect_byval.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
inline-asm-b128-test1.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
inline-asm-b128-test2.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
inline-asm-b128-test3.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
inline-asm.ll
[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#141711)
2025-05-29 12:24:31 -07:00
inlineasm-output-template.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
insertelt-dynamic.ll
[DAGCombiner] Lower dynamic insertelt chain more efficiently (#162368)
2025-10-29 09:46:01 -07:00
intr-range.ll
[NVPTX] Add ranges to intrinsic definitions, cleanup NVVMIntrRange (#138338)
2025-05-05 16:22:25 -07:00
intrinsic-old.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
intrinsics-sm90-ptx81.ll
[MLIR][NVPTX] Add intrinsics and Ops to read smem-sizes (#173089)
2025-12-21 19:29:24 +05:30
intrinsics-sm90.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
intrinsics.ll
[MLIR][NVPTX] Add intrinsics and Ops to read smem-sizes (#173089)
2025-12-21 19:29:24 +05:30
isspacep.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
jump-table.ll
[NVPTX] Fixup and refactor brx.idx support (#171933)
2025-12-12 11:36:15 -08:00
kernel-param-align.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
ld-addrspace.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
ld-generic.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
ld-param-sink.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
ld-st-addrrspace.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
ldg-invariant-256.ll
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
ldg-invariant.ll
[NVPTX] Use PRMT more widely, and improve folding around this instruction (#148261)
2025-07-13 15:06:53 -07:00
ldparam-v4.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
ldu-i8.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
ldu-ldg.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
ldu-reg-plus-offset.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
lit.local.cfg
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
load-sext-i1.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
load-store-256-addressing-invariant.ll
[NVPTX] legalize v2i32 to improve compatibility with v2f32 (#153478)
2025-09-26 13:52:11 -07:00
load-store-256-addressing.ll
[NVPTX] legalize v2i32 to improve compatibility with v2f32 (#153478)
2025-09-26 13:52:11 -07:00
load-store-atomic.err.ll
[NVPTX] Fixup some issues introduced by 128-bit atomics (#155921)
2025-08-28 14:43:54 -07:00
load-store-scalars.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
load-store-sm-70.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
load-store-sm-90.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
load-store-vectors-256.ll
[NVPTX] legalize v2i32 to improve compatibility with v2f32 (#153478)
2025-09-26 13:52:11 -07:00
load-store-vectors.ll
[NVPTX] Use PRMT more widely, and improve folding around this instruction (#148261)
2025-07-13 15:06:53 -07:00
load-with-non-coherent-cache.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
LoadStoreVectorizer.ll
[NVPTX] Update the default SM to 7.5 (#176021)
2026-01-22 18:26:55 +00:00
local-stack-frame.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
loop-vectorize.ll
…
lower-aggr-copies.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
lower-alloca.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
lower-args-alignment.ll
[NVPTXLowerArgs] Add align attribute to return value of addrspace.wrap intrinsic (#153889)
2025-08-19 11:13:57 -05:00
lower-args-gridconstant.ll
[NVPTX] Auto-upgrade nvvm.grid_constant to param attribute (#155489)
2025-08-27 16:32:28 -07:00
lower-args.ll
[NVPTXLowerArgs] Add align attribute to return value of addrspace.wrap intrinsic (#153889)
2025-08-19 11:13:57 -05:00
lower-byval-args.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
lower-ctor-dtor.ll
[NVPTX] Fix global destructor handling not working with a single dtor (#162537)
2025-10-08 18:13:48 -05:00
lower-kernel-ptr-arg.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
machine-sink.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
machinelicm-no-preheader.mir
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
MachineSink-call.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
MachineSink-convergent.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
managed.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
masked-load-3xhalf.ll
[LoadStoreVectorizer] Fill gaps in load/store chains to enable vectorization (#159388)
2025-12-08 15:57:17 -06:00
masked-load-vectors.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
masked-store-variable-mask.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
masked-store-vectors-256.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
match.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins-sm53-ptx42.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins-sm80-ptx70-autoupgrade.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins-sm80-ptx70-instcombine.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
math-intrins-sm80-ptx70.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins-sm86-ptx72-autoupgrade.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins-sm86-ptx72.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
math-intrins.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
max-align.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
maxclusterrank.ll
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
2025-02-26 08:45:27 -08:00
mbarrier_arr_relaxed.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_arr.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_tx.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm80_ptx70.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm80_ptx71.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx78.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx80.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx86.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
minmax-negative.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
misaligned-vector-ldst.ll
Reland "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines" (#155063)
2025-08-25 09:15:44 -07:00
misched_func_call.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
mixed-precision-fp.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
mma-no-sink-after-laneid-check.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
module-inline-asm.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
mulhi-intrins.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
mulwide.ll
Reland "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines" (#155063)
2025-08-25 09:15:44 -07:00
naked-fn-with-frame-pointer.ll
[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)
2025-06-25 11:42:21 -07:00
nanosleep.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
no-extra-parens.ll
[NVPTX] cleanup & canonicalize mov (#129344)
2025-03-23 14:53:00 -07:00
no-f32x2.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
no-stack-protector-libcall-error.ll
StackProtector: Use LibcallLoweringInfo analysis (#170329)
2026-01-18 07:12:17 +01:00
noduplicate-syncthreads.ll
Reland "[NVPTX] Unify and extend barrier{.cta} intrinsic support" (#141143)
2025-05-22 19:38:10 -07:00
nofunc.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
noreturn.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
nounroll.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
nvcl-param-align.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
nvptx-aa-inline-asm.ll
[NVPTX] Improve modeling of inline PTX (#130675)
2025-03-25 13:46:16 -07:00
nvptx-aa.ll
[NVPTX] Add support for Shared Cluster Memory address space [1/2] (#135444)
2025-04-22 15:14:39 -07:00
nvptx-fold-fma.ll
[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)
2025-12-09 22:39:11 +05:30
nvptx-prec-divf32-flag.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
NVPTXAA_before_BasicAA.ll
[NVPTX] Fix NVPTXAA_before_BasicAA Test (#138992)
2025-05-07 16:59:33 -07:00
nvvm-annotations-D120129.ll
…
nvvm-reflect-arch-O0.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
nvvm-reflect-arch.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-module-flag.ll
…
nvvm-reflect-ocl.ll
[NVPTX] Fix failing test and incorrect mcpu reading in reflect
2025-01-21 13:25:04 -06:00
nvvm-reflect-opaque.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
nvvm-reflect-options.ll
[NVPTX] Improve NVVMReflect Efficiency (#134416)
2025-04-10 18:33:37 -07:00
nvvm-reflect.ll
[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)
2025-01-07 14:45:03 -06:00
op-fence.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
packed-aggr.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
param-add.ll
[Support] Support debug counters in non-assertion builds (#170468)
2025-12-03 16:21:47 +01:00
param-align.ll
[NVPTX] Allow directly storing immediates to improve readability (#145552)
2025-06-25 18:46:39 -07:00
param-load-store.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
param-overalign.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
param-vectorize-device.ll
[NVPTX] Fix lit test issue from used_bytes_mask (#171220)
2025-12-08 19:35:02 -06:00
param-vectorize-kernel.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
pass-name.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pm-event.ll
[NVPTX] Print PM Event Mask value as unsigned integer. (#178891)
2026-02-03 07:49:58 +01:00
pow2_mask_cmp.ll
[NVPTX] Further cleanup call isel (#146411)
2025-07-01 14:55:04 -07:00
pr13291-i1-store.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
pr16278.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
pr17529.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
pr126337.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
prefetch-inferas-test.ll
[NVPTX] prefetch.tensormap pattern rewriter fix (#159253)
2025-09-24 15:29:41 +05:30
prefetch.ll
[NVPTX] prefetch.tensormap pattern rewriter fix (#159253)
2025-09-24 15:29:41 +05:30
prmt-const-folding.ll
[NVPTX] Add PRMT constant folding and cleanup usage of PRMT node (#148906)
2025-07-17 11:10:23 -07:00
prmt.ll
[NVPTX] Use prmt.f4e to lower pointer alignment fshr idiom (#143407)
2025-06-12 23:09:55 -07:00
proxy-reg-erasure-ptx.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
proxy-reg-erasure.mir
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
ptx-version-validation.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
rcp-opt.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
read-global-variable-constant.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
reduction-intrinsics.ll
[NVPTX] legalize v2i32 to improve compatibility with v2f32 (#153478)
2025-09-26 13:52:11 -07:00
redux-sync-f32.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
redux-sync.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
refl1.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-copy.ll
[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)
2025-01-07 18:24:50 -08:00
reg-types.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
rotate_64.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rotate-add.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rotate.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
rsqrt-opt.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
rsqrt.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
sad-intrins.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sched1.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sched2.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
setmaxnreg-sm100a.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
setmaxnreg.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
sext-in-reg.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
sext-params.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
sext-setcc.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
shfl-p.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
shfl-sync-p.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
shfl-sync.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
shfl.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
shift-opt.ll
[NVPTX][DagCombiner] Eliminate guards on shift amount because PTX shifts automatically clamp (#172431)
2025-12-17 12:13:36 -08:00
shift-parts.ll
[NVPTX] Add some more immediate instruction variants (#122746)
2025-01-14 21:28:29 -08:00
short-ptr.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
shuffle-vec-undef-init.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
simple-call.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
sm-version.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
speculative-execution-divergent-target.ll
…
sqrt-approx.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
st_bulk.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
st-addrspace.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
st-generic.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
st-param-imm.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
stackaddress.ll
[Clang] Add __builtin_stack_address (#148281)
2026-01-12 10:01:57 +01:00
stacksaverestore.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
store-retval.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
store-undef.ll
[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146930)
2025-07-28 10:41:51 -07:00
surf-read-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
surf-read.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
surf-tex.py
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
surf-write-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
surf-write.ll
Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)
2025-02-14 18:45:14 -08:00
switch-loop-header.mir
[MachineBasicBlock] Don't split loop header successor if the terminator is unanalyzable (#170146)
2025-12-03 15:55:59 +00:00
switch.ll
[NVPTX] Fixup and refactor brx.idx support (#171933)
2025-12-12 11:36:15 -08:00
symbol-naming.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
szext.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
tag-invariant-loads.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
TailDuplication-convergent.ll
…
tanhf.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
tcgen05-alloc.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-commit.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-cp.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-fence.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-ld-red.ll
[LLVM][NVPTX] Add support for tcgen05.ld.red Instruction (#175919)
2026-01-19 14:36:55 +05:30
tcgen05-ld.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-mma-block-scale-invalid.ll
[NVVM][NVPTX] Add support for tcgen05.mma (#151949)
2025-09-24 06:35:35 +05:30
tcgen05-mma-block-scale-ptx88-aa.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-block-scale-ptx88.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-block-scale.ll
[NVVM][NVPTX] Add support for tcgen05.mma (#151949)
2025-09-24 06:35:35 +05:30
tcgen05-mma-disable-output-lane-i8.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-disable-output-lane.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-i8.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-invalid.ll
[NVVM][NVPTX] Add support for tcgen05.mma (#151949)
2025-09-24 06:35:35 +05:30
tcgen05-mma-scale-d-invalid.ll
[NVVM][NVPTX] Add support for tcgen05.mma (#151949)
2025-09-24 06:35:35 +05:30
tcgen05-mma-scale-d.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-tensor-formatted.ll
[LLVM-Tablegen] Pretty Printing Arguments in LLVM Intrinsics (#162629)
2025-11-17 09:00:40 -08:00
tcgen05-mma-ws-i8.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-ws.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-shift.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tcgen05-st.ll
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
2025-10-13 19:26:32 +05:30
tensormap_replace_invalid.ll
[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)
2026-01-01 11:19:26 +05:30
tensormap_replace_sm_100a.ll
[NVPTX] Add missing preconditions to tensormap replace tests (#174190)
2026-01-02 16:34:06 +05:30
tensormap_replace_sm_103a.ll
[NVPTX] Add proper precondition in tensormap_replace_sm_103a test (#174144)
2026-01-01 12:30:01 -05:00
tensormap_replace.ll
[NVPTX] Add missing preconditions to tensormap replace tests (#174190)
2026-01-02 16:34:06 +05:30
tex-read-cuda.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
tex-read.ll
[NVPTX] Remove Float register classes (#140487)
2025-05-21 11:33:57 -07:00
texsurf-queries.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
thread-fence.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
tid-range.ll
[NVPTX] Rework and cleanup FTZ ISel (#146410)
2025-07-09 11:16:48 -07:00
trunc-setcc.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
trunc-tofp.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
unaligned-param-load-store.ll
[NVPTX] Skip numbering unreferenced virtual registers (readability) (#154391)
2025-08-19 12:27:46 -07:00
unfold-masked-merge-vector-variablemask.ll
[NVPTX] fold movs into loads and stores (#144581)
2025-06-24 16:02:13 -04:00
unreachable.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
unrecognized-sm1x.ll
[NVPTX] Require asserts in unrecognized-sm1x.ll (#126105)
2025-02-06 11:17:55 -08:00
upgrade-nvvm-annotations.ll
[NVPTX] Auto-upgrade nvvm.grid_constant to param attribute (#155489)
2025-08-27 16:32:28 -07:00
used-bytes-mask.ll
[NVPTX] Fix lit test issue from used_bytes_mask (#171220)
2025-12-08 19:35:02 -06:00
vaargs.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
variadics-backend.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
variadics-lowering.ll
[IR] Remove size argument from lifetime intrinsics (#150248)
2025-08-08 11:09:34 +02:00
vec8.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vec-param-load.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
vector-args.ll
[NVPTX] support f32x2 instructions for sm_100+ (#126337)
2025-07-11 11:50:50 -07:00
vector-call.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vector-compare.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
vector-global.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
vector-loads.ll
Partial revert "[NVPTX] Enhance mul.wide and mad.wide peepholes #150477" (#155024)
2025-08-25 22:11:18 +00:00
vector-returns.ll
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
vector-select.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
vector-stores.ll
[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt (#154476)
2025-08-21 10:30:36 -07:00
vectorize-misaligned.ll
[NVPTX] use untyped loads and stores where ever possible (#137698)
2025-05-10 08:26:26 -07:00
vote.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
weak-global.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
weak-linkage.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00
wgmma-sm90a-fence.ll
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx60-sm70.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx61-sm70.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx63-sm72.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx63-sm75.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx64-sm70.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx65-sm75.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx71-sm80.py
Reland "[lit] Refactor available ptxas features" (#155923)
2025-09-02 10:42:25 -07:00
wmma-ptx78-sm90.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx86-sm100a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx86-sm101a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx87-sm120a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm100f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm120a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm120f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx90-sm110f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
zeroext-32bit.ll
[NVPTX,test] Change llc -march= to -mtriple=
2024-12-15 10:45:11 -08:00