2906fcadb8
into zext x LegalizerHelper has two padding strategies: undef or zero. see LegalizerHelper:273 see LegalizerHelper:315 This PR is about zero sugar and Coke Zero. ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](s32) Please continue padding merge values. // %bits_8_15:(s8) = G_CONSTANT i8 0 // %0:(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8) %bits_8_15 is defined by zero. For optimization, we pick zext. // %0:_(s16) = G_ZEXT %bits_0_7:(s8) The upper bits of %0 are zero and the lower bits come from %bits_0_7.
87 lines
2.6 KiB
C++
87 lines
2.6 KiB
C++
//===- CombinerHelperArtifacts.cpp-----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements CombinerHelper for legalization artifacts.
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//
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//===----------------------------------------------------------------------===//
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//
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// G_MERGE_VALUES
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/LowLevelTypeUtils.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/Support/Casting.h"
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#define DEBUG_TYPE "gi-combiner"
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using namespace llvm;
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bool CombinerHelper::matchMergeXAndUndef(const MachineInstr &MI,
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BuildFnTy &MatchInfo) {
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const GMerge *Merge = cast<GMerge>(&MI);
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Register Dst = Merge->getReg(0);
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LLT DstTy = MRI.getType(Dst);
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LLT SrcTy = MRI.getType(Merge->getSourceReg(0));
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// Otherwise, we would miscompile.
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assert(Merge->getNumSources() == 2 && "Unexpected number of operands");
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//
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// %bits_8_15:_(s8) = G_IMPLICIT_DEF
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// %0:_(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8)
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//
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// ->
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//
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// %0:_(s16) = G_ANYEXT %bits_0_7:(s8)
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//
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if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ANYEXT, {DstTy, SrcTy}}))
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return false;
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MatchInfo = [=](MachineIRBuilder &B) {
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B.buildAnyExt(Dst, Merge->getSourceReg(0));
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};
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return true;
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}
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bool CombinerHelper::matchMergeXAndZero(const MachineInstr &MI,
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BuildFnTy &MatchInfo) {
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const GMerge *Merge = cast<GMerge>(&MI);
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Register Dst = Merge->getReg(0);
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LLT DstTy = MRI.getType(Dst);
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LLT SrcTy = MRI.getType(Merge->getSourceReg(0));
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// No multi-use check. It is a constant.
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//
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// %bits_8_15:_(s8) = G_CONSTANT i8 0
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// %0:_(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8)
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//
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// ->
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//
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// %0:_(s16) = G_ZEXT %bits_0_7:(s8)
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//
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if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}}))
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return false;
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MatchInfo = [=](MachineIRBuilder &B) {
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B.buildZExt(Dst, Merge->getSourceReg(0));
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};
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return true;
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}
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