241 lines
9.4 KiB
TableGen
241 lines
9.4 KiB
TableGen
//===-- VINTERPInstructions.td - VINTERP Instruction Definitions ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VINTERP encoding
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//===----------------------------------------------------------------------===//
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class VINTERPe <VOPProfile P> : Enc64 {
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bits<11> vdst;
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bits<4> src0_modifiers;
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bits<11> src0;
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bits<3> src1_modifiers;
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bits<11> src1;
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bits<3> src2_modifiers;
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bits<11> src2;
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bits<1> clamp;
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bits<3> waitexp;
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let Inst{31-26} = 0x33; // VOP3P encoding
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let Inst{25-24} = 0x1; // VINTERP sub-encoding
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let Inst{7-0} = vdst{7-0};
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let Inst{10-8} = waitexp;
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// Fields for hi/lo 16-bits of register selection
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let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
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let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
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let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
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let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
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let Inst{15} = clamp;
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let Inst{40-32} = src0{8-0};
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let Inst{49-41} = src1{8-0};
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let Inst{58-50} = src2{8-0};
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let Inst{61} = src0_modifiers{0}; // neg(0)
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let Inst{62} = src1_modifiers{0}; // neg(1)
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let Inst{63} = src2_modifiers{0}; // neg(2)
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}
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class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : VINTERPe<P> {
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let Inst{22-16} = op;
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}
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class VINTERPe_gfx12 <bits<7> op, VOPProfile P> : VINTERPe<P> {
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let Inst{20-16} = op{4-0};
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}
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//===----------------------------------------------------------------------===//
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// VOP3 VINTERP
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//===----------------------------------------------------------------------===//
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class VINTERP_Pseudo <string OpName, VOPProfile P, list<dag> pattern = []> :
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VOP3_Pseudo<OpName, P, pattern, 0, 0> {
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let AsmMatchConverter = "cvtVINTERP";
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let mayRaiseFPException = 0;
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let VOP3_OPSEL = 1;
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let VINTERP = 1;
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}
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class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily, string asmName> :
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VOP3_Real <ps, EncodingFamily, asmName> {
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let VINTERP = 1;
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let IsSingle = 1;
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}
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def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
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let HasOpSel = 0;
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let HasModifiers = 1;
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let Src0Mod = FPVRegInputMods;
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let Src1Mod = FPVRegInputMods;
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let Src2Mod = FPVRegInputMods;
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let Outs64 = (outs VGPR_32:$vdst);
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let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
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Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
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Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
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Clamp:$clamp,
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WaitEXP:$waitexp);
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let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
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}
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class VOP3_VINTERP_F16_t16 <list<ValueType> ArgVT> : VOPProfile_True16<VOPProfile<ArgVT>> {
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let Src0Mod = FPT16VRegInputMods</*Fake16*/0>;
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let Src1Mod = FPVRegInputMods;
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let Src2Mod = !if(!eq(ArgVT[3].Size, 16), FPT16VRegInputMods</*Fake16*/0>,
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FPVRegInputMods);
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let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_16:$src0,
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Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
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Src2Mod:$src2_modifiers,
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!if(!eq(ArgVT[3].Size, 16), VRegSrc_16, VRegSrc_32):$src2,
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Clamp:$clamp, op_sel0:$op_sel,
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WaitEXP:$waitexp);
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let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
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}
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class VOP3_VINTERP_F16_fake16 <list<ValueType> ArgVT> : VOPProfile_Fake16<VOPProfile<ArgVT>> {
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let Src0Mod = FPT16VRegInputMods</*Fake16*/1>;
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let Src1Mod = FPVRegInputMods;
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let Src2Mod = !if(!eq(ArgVT[3].Size, 16), FPT16VRegInputMods</*Fake16*/1>,
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FPVRegInputMods);
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let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_fake16:$src0,
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Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
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Src2Mod:$src2_modifiers,
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!if(!eq(ArgVT[3].Size, 16), VRegSrc_fake16, VRegSrc_32):$src2,
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Clamp:$clamp, op_sel0:$op_sel,
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WaitEXP:$waitexp);
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let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
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}
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//===----------------------------------------------------------------------===//
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// VINTERP Pseudo Instructions
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = HasVINTERPEncoding in {
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multiclass VINTERP_t16<string OpName, list<ValueType> ArgVT> {
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let True16Predicate = UseRealTrue16Insts in {
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def _t16 : VINTERP_Pseudo<OpName#"_t16", VOP3_VINTERP_F16_t16<ArgVT>> ;
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}
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let True16Predicate = UseFakeTrue16Insts in {
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def _fake16 : VINTERP_Pseudo<OpName#"_fake16", VOP3_VINTERP_F16_fake16<ArgVT>> ;
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}
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}
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let Uses = [M0, EXEC, MODE] in {
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def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
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def V_INTERP_P2_F32_inreg : VINTERP_Pseudo <"v_interp_p2_f32", VOP3_VINTERP_F32>;
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defm V_INTERP_P10_F16_F32_inreg : VINTERP_t16<"v_interp_p10_f16_f32", [f32, f16, f32, f16]>;
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defm V_INTERP_P2_F16_F32_inreg : VINTERP_t16<"v_interp_p2_f16_f32", [f16, f16, f32, f32]>;
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} // Uses = [M0, EXEC, MODE]
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let Uses = [M0, EXEC] in {
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defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_t16<"v_interp_p10_rtz_f16_f32", [f32, f16, f32, f16]>;
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defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_t16 <"v_interp_p2_rtz_f16_f32", [f16, f16, f32, f32]>;
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} // Uses = [M0, EXEC]
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} // SubtargetPredicate = HasVINTERPEncoding.
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class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
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(f32 (op
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(VINTERPMods f32:$src0, i32:$src0_modifiers),
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(VINTERPMods f32:$src1, i32:$src1_modifiers),
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(VINTERPMods f32:$src2, i32:$src2_modifiers))),
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(inst $src0_modifiers, $src0,
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$src1_modifiers, $src1,
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$src2_modifiers, $src2,
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0, /* clamp */
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7) /* wait_exp */
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>;
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class VInterpF16Pat <SDPatternOperator op, Instruction inst,
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ValueType dst_type, bit high,
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list<ComplexPattern> pat> : GCNPat <
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(dst_type (op
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(pat[0] f32:$src0, i32:$src0_modifiers),
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(pat[1] f32:$src1, i32:$src1_modifiers),
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(pat[2] f32:$src2, i32:$src2_modifiers),
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!if(high, (i1 -1), (i1 0)))),
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(inst $src0_modifiers, $src0,
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$src1_modifiers, $src1,
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$src2_modifiers, $src2,
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0, /* clamp */
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/* op_sel = 0 */
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7) /* wait_exp */
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>;
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multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
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ValueType dst_type, list<ComplexPattern> high_pat> {
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def : VInterpF16Pat<op, inst, dst_type, 0,
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[VINTERPMods, VINTERPMods, VINTERPMods]>;
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def : VInterpF16Pat<op, inst, dst_type, 1, high_pat>;
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}
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def : VInterpF32Pat<int_amdgcn_interp_inreg_p10, V_INTERP_P10_F32_inreg>;
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def : VInterpF32Pat<int_amdgcn_interp_inreg_p2, V_INTERP_P2_F32_inreg>;
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let True16Predicate = UseFakeTrue16Insts in {
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defm : VInterpF16Pat<int_amdgcn_interp_inreg_p10_f16,
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V_INTERP_P10_F16_F32_inreg_fake16, f32,
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[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
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defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
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V_INTERP_P2_F16_F32_inreg_fake16, f16,
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[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
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defm : VInterpF16Pat<int_amdgcn_interp_p10_rtz_f16,
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V_INTERP_P10_RTZ_F16_F32_inreg_fake16, f32,
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[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
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defm : VInterpF16Pat<int_amdgcn_interp_p2_rtz_f16,
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V_INTERP_P2_RTZ_F16_F32_inreg_fake16, f16,
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[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
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}
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//===----------------------------------------------------------------------===//
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// VINTERP Real Instructions
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//===----------------------------------------------------------------------===//
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multiclass VINTERP_Real_gfx11 <bits<7> op, string asmName> {
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defvar ps = !cast<VOP3_Pseudo>(NAME);
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let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" #
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!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
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def _gfx11 :
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VINTERP_Real<ps, SIEncodingFamily.GFX11, asmName>,
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VINTERPe_gfx11<op, ps.Pfl>;
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}
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}
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multiclass VINTERP_Real_gfx12 <bits<7> op, string asmName> {
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defvar ps = !cast<VOP3_Pseudo>(NAME);
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let AssemblerPredicate = isGFX12Only, DecoderNamespace = "GFX12" #
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!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
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def _gfx12 :
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VINTERP_Real<ps, SIEncodingFamily.GFX12, asmName>,
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VINTERPe_gfx12<op, ps.Pfl>;
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}
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}
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multiclass VINTERP_Real_gfx11_gfx12 <bits<7> op, string asmName = !cast<VOP3_Pseudo>(NAME).Mnemonic> :
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VINTERP_Real_gfx11<op, asmName>, VINTERP_Real_gfx12<op, asmName>;
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multiclass VINTERP_Real_t16_and_fake16_gfx11_gfx12 <bits<7> op, string asmName = !cast<VOP3_Pseudo>(NAME).Mnemonic> {
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defm _t16: VINTERP_Real_gfx11_gfx12<op, asmName>;
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defm _fake16: VINTERP_Real_gfx11_gfx12<op, asmName>;
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}
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defm V_INTERP_P10_F32_inreg : VINTERP_Real_gfx11_gfx12<0x000>;
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defm V_INTERP_P2_F32_inreg : VINTERP_Real_gfx11_gfx12<0x001>;
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defm V_INTERP_P10_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x002, "v_interp_p10_f16_f32">;
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defm V_INTERP_P2_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x003, "v_interp_p2_f16_f32">;
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defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x004, "v_interp_p10_rtz_f16_f32">;
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defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x005, "v_interp_p2_rtz_f16_f32">;
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