b01c006f73
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case. This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
107 lines
4.3 KiB
C++
107 lines
4.3 KiB
C++
//===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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#include "ARCRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "ARCGenInstrInfo.inc"
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namespace llvm {
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class ARCSubtarget;
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class ARCInstrInfo : public ARCGenInstrInfo {
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const ARCRegisterInfo RI;
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virtual void anchor();
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public:
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ARCInstrInfo(const ARCSubtarget &);
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const ARCRegisterInfo &getRegisterInfo() const { return RI; }
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/// If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &,
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int *BytesAdded = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc, bool RenamableDest = false,
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bool RenamableSrc = false) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register SrcReg,
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bool IsKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isPostIncrement(const MachineInstr &MI) const override;
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// ARC-specific
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bool isPreIncrement(const MachineInstr &MI) const;
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virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
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unsigned &BasePos,
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unsigned &OffsetPos) const override;
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// Emit code before MBBI to load immediate value into physical register Reg.
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// Returns an iterator to the new instruction.
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MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned Reg, uint64_t Value) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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