cc3bb85580
The Pre-RA VLIWMachineScheduler used by Hexagon is a relatively generic implementation that would make sense to use on other VLIW targets. This commit lifts those classes into their own header/source file with the root VLIWMachineScheduler. I chose this path rather than adding the strategy et al. into MachineScheduler to avoid bloating the file with other implementations. Target-specific behaviors have been captured and replicated through function overloads. - Added an overloadable DFAPacketizer creation member function. This is mainly done for our downstream, which has the capability to override the DFAPacketizer with custom implementations. This is an upstreamable TODO on our end. Currently, it always returns the result of TargetInstrInfo::CreateTargetScheduleState - Added an extra helper which returns the number of instructions in the current packet. This is used in our downstream, and may be useful elsewhere. - Placed the priority heuristic values into the ConvergingVLIWscheduler class instead of defining them as local statics in the implementation - Added a overridable helper in ConvergingVLIWScheduler so that targets can create their own VLIWResourceModel Differential Revision: https://reviews.llvm.org/D113150
71 lines
2.5 KiB
C++
71 lines
2.5 KiB
C++
//===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineScheduler schedules machine instructions after phi elimination. It
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// preserves LiveIntervals so it can be invoked before register allocation.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMachineScheduler.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/VLIWMachineScheduler.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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/// Return true if there is a dependence between SUd and SUu.
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bool HexagonVLIWResourceModel::hasDependence(const SUnit *SUd,
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const SUnit *SUu) {
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const auto *QII = static_cast<const HexagonInstrInfo *>(TII);
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// Enable .cur formation.
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if (QII->mayBeCurLoad(*SUd->getInstr()))
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return false;
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if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
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return false;
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return VLIWResourceModel::hasDependence(SUd, SUu);
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}
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VLIWResourceModel *HexagonConvergingVLIWScheduler::createVLIWResourceModel(
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const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const {
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return new HexagonVLIWResourceModel(STI, SchedModel);
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}
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int HexagonConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
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SchedCandidate &Candidate,
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RegPressureDelta &Delta,
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bool verbose) {
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int ResCount =
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ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, Delta, verbose);
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if (!SU || SU->isScheduled)
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return ResCount;
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auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
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auto &QII = *QST.getInstrInfo();
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if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
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if (Q.getID() == TopQID &&
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Top.ResourceModel->isResourceAvailable(SU, true)) {
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ResCount += PriorityTwo;
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LLVM_DEBUG(if (verbose) dbgs() << "C|");
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} else if (Q.getID() == BotQID &&
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Bot.ResourceModel->isResourceAvailable(SU, false)) {
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ResCount += PriorityTwo;
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LLVM_DEBUG(if (verbose) dbgs() << "C|");
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}
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}
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return ResCount;
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}
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