c4c9d4f306
Add support for the moveq instruction, which is both faster and smaller (1/2 to 1/3 the size) than a move with immediate to register. This change introduces the instruction, along with a set of pseudoinstructions to handle immediate moves to a register that is lowered post-RA. Pseudos are used as moveq can only write to the full register, which makes matching i8 and i16 immediate loads difficult in tablegen. Furthermore, selecting moveq before RA constrains that immediate to be moved into a data register, which may not be optimal. The bulk of this change are fixes to existing tests, which cover the new functionality sufficiently.
759 lines
30 KiB
TableGen
759 lines
30 KiB
TableGen
//===-- M68kInstrData.td - M68k Data Movement Instructions -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes the Motorola 680x0 data movement instructions which are
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/// the basic means of transferring and storing addresses and data. Here is the
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/// current status of the file:
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///
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/// Machine:
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///
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/// EXG [ ] FMOVE [ ] FSMOVE [ ] FDMOVE [ ] FMOVEM [ ]
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/// LEA [~] PEA [ ] MOVE [~] MOVE16 [ ] MOVEA [ ]
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/// MOVEM [ ] MOVEP [ ] MOVEQ [ ] LINK [~] UNLK [~]
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///
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/// Pseudo:
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///
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/// MOVI [x] MOVSX [x] MOVZX [x] MOVX [x]
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///
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/// Map:
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///
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/// [ ] - was not touched at all
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/// [!] - requires extarnal stuff implemented
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/// [~] - in progress but usable
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/// [x] - done
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MOVE
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//===----------------------------------------------------------------------===//
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/// -----------------------------------------------------
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/// F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
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/// -----------------------------------------------------
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/// | | DESTINATION | SOURCE
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/// 0 0 | SIZE | REG | MODE | MODE | REG
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/// -----------------------------------------------------
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///
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/// NOTE Move requires EA X version for direct register destination(0)
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// MOVE has a different size encoding.
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class MxMoveSize<bits<2> value> {
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bits<2> Value = value;
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}
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def MxMoveSize8 : MxMoveSize<0b01>;
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def MxMoveSize16 : MxMoveSize<0b11>;
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def MxMoveSize32 : MxMoveSize<0b10>;
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class MxMoveEncoding<MxMoveSize size, MxEncMemOp dst_enc, MxEncMemOp src_enc> {
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dag Value = (ascend
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(descend 0b00, size.Value,
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!cond(
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!eq(!getdagop(dst_enc.EA), descend): !setdagop(dst_enc.EA, ascend),
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!eq(!getdagop(dst_enc.EA), ascend): !setdagop(dst_enc.EA, descend)),
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src_enc.EA),
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// Source extension
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src_enc.Supplement,
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// Destination extension
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dst_enc.Supplement
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);
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}
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// Special encoding for Xn
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class MxMoveEncAddrMode_r<string reg_opnd> : MxEncMemOp {
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let EA = (descend (descend 0b00, (slice "$"#reg_opnd, 3, 3)),
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(operand "$"#reg_opnd, 3));
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}
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// TODO: Generalize and adopt this utility in other .td files as well.
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multiclass MxMoveOperandEncodings<string opnd_name> {
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// Dn
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def MxMove#NAME#OpEnc_d : MxEncAddrMode_d<opnd_name>;
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// An
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def MxMove#NAME#OpEnc_a : MxEncAddrMode_a<opnd_name>;
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// Xn
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def MxMove#NAME#OpEnc_r : MxMoveEncAddrMode_r<opnd_name>;
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// (An)+
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def MxMove#NAME#OpEnc_o : MxEncAddrMode_o<opnd_name>;
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// -(An)
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def MxMove#NAME#OpEnc_e : MxEncAddrMode_e<opnd_name>;
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// (i,PC,Xn)
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def MxMove#NAME#OpEnc_k : MxEncAddrMode_k<opnd_name>;
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// (i,PC)
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def MxMove#NAME#OpEnc_q : MxEncAddrMode_q<opnd_name>;
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// (i,An,Xn)
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def MxMove#NAME#OpEnc_f : MxEncAddrMode_f<opnd_name>;
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// (i,An)
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def MxMove#NAME#OpEnc_p : MxEncAddrMode_p<opnd_name>;
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// (ABS).L
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def MxMove#NAME#OpEnc_b : MxEncAddrMode_abs<opnd_name, /*W/L=*/true>;
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// (An)
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def MxMove#NAME#OpEnc_j : MxEncAddrMode_j<opnd_name>;
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}
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defm Src : MxMoveOperandEncodings<"src">;
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defm Dst : MxMoveOperandEncodings<"dst">;
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defvar MxMoveSupportedAMs = ["o", "e", "k", "q", "f", "p", "b", "j"];
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let Defs = [CCR] in
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class MxMove<string size, dag outs, dag ins, list<dag> pattern, MxMoveEncoding enc>
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: MxInst<outs, ins, "move."#size#"\t$src, $dst", pattern> {
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let Inst = enc.Value;
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}
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// R <- R
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class MxMove_RR<MxType TYPE, string DST_REG, string SRC_REG,
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MxMoveEncoding ENC,
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG),
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MxOpBundle SRC = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_REG)>
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: MxMove<TYPE.Prefix,
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(outs DST.Op:$dst), (ins SRC.Op:$src),
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[(null_frag)], ENC>;
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foreach DST_REG = ["r", "a"] in {
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foreach SRC_REG = ["r", "a"] in
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foreach TYPE = [MxType16, MxType32] in
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def MOV # TYPE.Size # DST_REG # SRC_REG # TYPE.Postfix
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: MxMove_RR<TYPE, DST_REG, SRC_REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_REG),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#SRC_REG)>>;
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} // foreach DST_REG
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foreach TYPE = [MxType8, MxType16, MxType32] in
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def MOV # TYPE.Size # dd # TYPE.Postfix
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: MxMove_RR<TYPE, "d", "d",
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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MxMoveDstOpEnc_d, MxMoveSrcOpEnc_d>>;
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// M <- R
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let mayStore = 1 in {
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class MxMove_MR<MxType TYPE, MxOpBundle DST, string SRC_REG, MxMoveEncoding ENC,
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MxOpBundle SRC = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_REG)>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store TYPE.VT:$src, DST.Pat:$dst)], ENC>;
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class MxMove_MI<MxType TYPE, MxOpBundle DST, MxMoveEncoding ENC,
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MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i")>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store SRC.ImmPat:$src, DST.Pat:$dst)], ENC>;
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} // let mayStore = 1
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foreach REG = ["r", "a", "d"] in
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # AM # REG # TYPE.Postfix
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: MxMove_MR<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM), REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#REG)>>;
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} // foreach AM
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType8, MxType16, MxType32] in
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def MOV # TYPE.Size # AM # i # TYPE.Postfix
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: MxMove_MI<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM),
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MxEncAddrMode_i<"src", TYPE.Size>>>;
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} // foreach AM
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// R <- I
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// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
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class MxMove_RI<MxType TYPE, string DST_REG, MxMoveEncoding ENC,
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MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i"),
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG)>
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: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
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[(null_frag)], ENC>;
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foreach REG = ["r", "a", "d"] in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # REG # i # TYPE.Postfix
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: MxMove_RI<TYPE, REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#REG),
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MxEncAddrMode_i<"src", TYPE.Size>>>;
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} // foreach REG
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// R <- M
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let mayLoad = 1 in
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class MxMove_RM<MxType TYPE, string DST_REG, MxOpBundle SRC, MxEncMemOp SRC_ENC,
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MxMoveSize SIZE_ENC = !cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG),
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MxEncMemOp DST_ENC = !cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_REG)>
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: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
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[(set TYPE.VT:$dst, (TYPE.Load SRC.Pat:$src))],
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MxMoveEncoding<SIZE_ENC, DST_ENC, SRC_ENC>>;
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foreach REG = ["r", "a", "d"] in
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # REG # AM # TYPE.Postfix
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: MxMove_RM<TYPE, REG, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
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} // foreach AM
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// Tail call version
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let Pattern = [(null_frag)] in {
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foreach REG = ["r", "a"] in
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType16, MxType32] in
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def MOV # TYPE.Size # REG # AM # _TC
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: MxMove_RM<TYPE, REG, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)> {
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let isCodeGenOnly = true;
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}
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} // foreach AM
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} // let Pattern
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let mayLoad = 1, mayStore = 1 in
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class MxMove_MM<MxType TYPE, MxOpBundle DST, MxOpBundle SRC,
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MxEncMemOp DST_ENC, MxEncMemOp SRC_ENC>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store (TYPE.Load SRC.Pat:$src), DST.Pat:$dst)],
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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DST_ENC, SRC_ENC>>;
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foreach DST_AM = MxMoveSupportedAMs in
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foreach SRC_AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType8, MxType16, MxType32] in
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def MOV # TYPE.Size # DST_AM # SRC_AM # TYPE.Postfix
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: MxMove_MM<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_AM),
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!cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_AM),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#SRC_AM)>;
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} // foreach SRC_AM
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// Store ABS(basically pointer) as Immdiate to Mem
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def : Pat<(store MxType32.BPat :$src, MxType32.PPat :$dst),
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(MOV32pi MxType32.POp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.FPat :$dst),
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(MOV32fi MxType32.FOp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst),
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(MOV32bi MxType32.BOp :$dst, MxType32.IOp :$src)>;
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def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst),
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(MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>;
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//===----------------------------------------------------------------------===//
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// MOVEQ
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//===----------------------------------------------------------------------===//
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/// ------------+---------+---+-----------------------
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/// F E D C | B A 9 | 8 | 7 6 5 4 3 2 1 0
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/// ------------+---------+---+-----------------------
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/// 0 1 1 1 | REG | 0 | DATA
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/// ------------+---------+---+-----------------------
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// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
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let Defs = [CCR] in
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def MOVQ : MxInst<(outs MxDRD32:$dst), (ins Mxi8imm:$imm),
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"moveq\t$imm, $dst",
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[(null_frag)]> {
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let Inst = (descend 0b0111, (operand "$dst", 3), 0b0, (operand "$imm", 8));
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}
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//===----------------------------------------------------------------------===//
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// MOVEM
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//
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// The mask is already pre-processed by the save/restore spill hook
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//===----------------------------------------------------------------------===//
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// Direction
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defvar MxMOVEM_MR = false;
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defvar MxMOVEM_RM = true;
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// Size
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defvar MxMOVEM_W = false;
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defvar MxMOVEM_L = true;
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/// ---------------+-------------+-------------+---------
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/// F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0
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/// ---------------+---+---------+---+---------+---------
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/// 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG
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/// ---------------+---+---------+---+---------+---------
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/// REGISTER LIST MASK
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/// -----------------------------------------------------
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/// D - direction(RM,MR)
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/// S - size(W,L)
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class MxMOVEMEncoding<MxEncMemOp opnd_enc, bit size, bit direction,
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string mask_op_name> {
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dag Value = (ascend
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(descend 0b01001, direction, 0b001, size, opnd_enc.EA),
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// Mask
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(operand "$"#mask_op_name, 16),
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opnd_enc.Supplement
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);
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}
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let mayStore = 1 in
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class MxMOVEM_MR<MxType TYPE, bit SIZE_ENC,
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MxOperand MEMOp, MxEncMemOp MEM_ENC>
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: MxInst<(outs), (ins MEMOp:$dst, MxMoveMask:$mask),
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"movem."#TYPE.Prefix#"\t$mask, $dst", []> {
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let Inst = MxMOVEMEncoding<MEM_ENC, SIZE_ENC, MxMOVEM_MR, "mask">.Value;
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}
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType16, MxType32] in
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def MOVM # TYPE.Size # AM # m # TYPE.Postfix
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: MxMOVEM_MR<TYPE, !if(!eq(TYPE, MxType16), MxMOVEM_W, MxMOVEM_L),
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!cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM).Op,
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM)>;
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} // foreach AM
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let mayLoad = 1 in
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class MxMOVEM_RM<MxType TYPE, bit SIZE_ENC,
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MxOperand MEMOp, MxEncMemOp MEM_ENC>
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: MxInst<(outs), (ins MxMoveMask:$mask, MEMOp:$src),
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"movem."#TYPE.Prefix#"\t$src, $mask", []> {
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let Inst = MxMOVEMEncoding<MEM_ENC, SIZE_ENC, MxMOVEM_RM, "mask">.Value;
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}
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType16, MxType32] in
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def MOVM # TYPE.Size # m # AM # TYPE.Postfix
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: MxMOVEM_RM<TYPE, !if(!eq(TYPE, MxType16), MxMOVEM_W, MxMOVEM_L),
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!cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM).Op,
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
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} // foreach AM
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// Pseudo versions. These a required by virtual register spill/restore since
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// the mask requires real register to encode. These instruction will be expanded
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// into real MOVEM after RA finishes.
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let mayStore = 1 in
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class MxMOVEM_MR_Pseudo<MxType TYPE, MxOperand MEMOp>
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: MxPseudo<(outs), (ins MEMOp:$dst, TYPE.ROp:$reg)>;
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let mayLoad = 1 in
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class MxMOVEM_RM_Pseudo<MxType TYPE, MxOperand MEMOp>
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: MxPseudo<(outs TYPE.ROp:$dst), (ins MEMOp:$src)>;
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// Mem <- Reg
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def MOVM8jm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.JOp>;
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def MOVM16jm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.JOp>;
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def MOVM32jm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.JOp>;
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def MOVM8pm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.POp>;
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def MOVM16pm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.POp>;
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def MOVM32pm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.POp>;
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// Reg <- Mem
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def MOVM8mj_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.JOp>;
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def MOVM16mj_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.JOp>;
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def MOVM32mj_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.JOp>;
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def MOVM8mp_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.POp>;
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def MOVM16mp_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.POp>;
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def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
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//===----------------------------------------------------------------------===//
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// MOVE to/from SR/CCR
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//
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// A special care must be taken working with to/from CCR since it is basically
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// word-size SR register truncated for user mode thus it only supports word-size
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// instructions. Plus the original M68000 does not support moves from CCR. So in
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// order to use CCR effectively one MUST use proper byte-size pseudo instructi-
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// ons that will be resolved sometime after RA pass.
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//===----------------------------------------------------------------------===//
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/// --------------------------------------------------
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/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
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/// --------------------------------------------------
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/// | EFFECTIVE ADDRESS
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/// 0 1 0 0 0 1 0 0 1 1 | MODE | REG
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/// --------------------------------------------------
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let Defs = [CCR] in
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|
class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
|
|
: MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
|
|
let Inst = (ascend
|
|
(descend 0b0100010011, SRC_ENC.EA),
|
|
SRC_ENC.Supplement
|
|
);
|
|
}
|
|
|
|
class MxMoveToCCRPseudo<MxOperand MEMOp>
|
|
: MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
|
|
|
|
let mayLoad = 1 in
|
|
foreach AM = MxMoveSupportedAMs in {
|
|
def MOV16c # AM : MxMoveToCCR<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
|
|
!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
|
|
def MOV8c # AM : MxMoveToCCRPseudo<!cast<MxOpBundle>("MxOp8AddrMode_"#AM).Op>;
|
|
} // foreach AM
|
|
|
|
// Only data register is allowed.
|
|
def MOV16cd : MxMoveToCCR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
|
|
def MOV8cd : MxMoveToCCRPseudo<MxOp8AddrMode_d.Op>;
|
|
|
|
/// Move from CCR
|
|
/// --------------------------------------------------
|
|
/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
|
|
/// --------------------------------------------------
|
|
/// | EFFECTIVE ADDRESS
|
|
/// 0 1 0 0 0 0 1 0 1 1 | MODE | REG
|
|
/// --------------------------------------------------
|
|
let Uses = [CCR] in {
|
|
class MxMoveFromCCR_R
|
|
: MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
|
|
Requires<[ AtLeastM68010 ]> {
|
|
let Inst = (descend 0b0100001011, MxEncAddrMode_d<"dst">.EA);
|
|
}
|
|
|
|
class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
|
|
: MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []>,
|
|
Requires<[ AtLeastM68010 ]> {
|
|
let Inst = (ascend
|
|
(descend 0b0100001011, DST_ENC.EA),
|
|
DST_ENC.Supplement
|
|
);
|
|
}
|
|
|
|
class MxMoveFromCCRPseudo<MxOperand MEMOp>
|
|
: MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
|
|
} // let Uses = [CCR]
|
|
|
|
let mayStore = 1 in
|
|
foreach AM = MxMoveSupportedAMs in {
|
|
def MOV16 # AM # c
|
|
: MxMoveFromCCR_M<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
|
|
!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM)>;
|
|
def MOV8 # AM # c
|
|
: MxMoveFromCCRPseudo<!cast<MxOpBundle>("MxOp8AddrMode_"#AM).Op>;
|
|
} // foreach AM
|
|
|
|
// Only data register is allowed.
|
|
def MOV16dc : MxMoveFromCCR_R;
|
|
def MOV8dc : MxMoveFromCCRPseudo<MxOp8AddrMode_d.Op>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LEA
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ----------------------------------------------------
|
|
/// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
|
|
/// ----------------------------------------------------
|
|
/// 0 1 0 0 | DST REG | 1 1 1 | MODE | REG
|
|
/// ----------------------------------------------------
|
|
class MxLEA<MxOpBundle SRC, MxEncMemOp SRC_ENC>
|
|
: MxInst<(outs MxARD32:$dst), (ins SRC.Op:$src),
|
|
"lea\t$src, $dst", [(set i32:$dst, SRC.Pat:$src)]> {
|
|
let Inst = (ascend
|
|
(descend 0b0100, (operand "$dst", 3), 0b111, SRC_ENC.EA),
|
|
SRC_ENC.Supplement
|
|
);
|
|
}
|
|
|
|
foreach AM = ["p", "f", "b", "q", "k"] in
|
|
def LEA32 # AM : MxLEA<!cast<MxOpBundle>("MxOp32AddrMode_"#AM),
|
|
!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LINK/UNLK
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Uses = [SP], Defs = [SP] in {
|
|
let mayStore = 1 in {
|
|
|
|
def LINK16 : MxInst<(outs), (ins MxARD16:$src, Mxi16imm:$disp), "link.w\t$src, $disp", []> {
|
|
let Inst = (ascend
|
|
(descend 0b0100111001010, (operand "$src", 3)),
|
|
(operand "$disp", 16)
|
|
);
|
|
}
|
|
|
|
def LINK32 : MxInst<(outs), (ins MxARD16:$src, Mxi32imm:$disp), "link.l\t$src, $disp", []> {
|
|
let Inst = (ascend
|
|
(descend 0b0100100000001, (operand "$src", 3)),
|
|
(slice "$disp", 31, 16),
|
|
(slice "$disp", 15, 0)
|
|
);
|
|
}
|
|
|
|
def UNLK : MxInst<(outs), (ins MxARD32:$src), "unlk\t$src", []> {
|
|
let Inst = (descend 0b0100111001011, (operand "$src", 3));
|
|
}
|
|
|
|
} // let mayStore = 1
|
|
} // let Uses = [SP], Defs = [SP]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudos
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Pushe/Pop to/from SP for simplicity
|
|
let Uses = [SP], Defs = [SP], hasSideEffects = 0 in {
|
|
|
|
// SP <- SP - <size>; (SP) <- Dn
|
|
let mayStore = 1 in {
|
|
def PUSH8d : MxPseudo<(outs), (ins DR8:$reg)>;
|
|
def PUSH16d : MxPseudo<(outs), (ins DR16:$reg)>;
|
|
def PUSH32r : MxPseudo<(outs), (ins XR32:$reg)>;
|
|
} // let mayStore = 1
|
|
|
|
// Dn <- (SP); SP <- SP + <size>
|
|
let mayLoad = 1 in {
|
|
def POP8d : MxPseudo<(outs DR8:$reg), (ins)>;
|
|
def POP16d : MxPseudo<(outs DR16:$reg), (ins)>;
|
|
def POP32r : MxPseudo<(outs XR32:$reg), (ins)>;
|
|
} // let mayLoad = 1
|
|
|
|
} // let Uses/Defs = [SP], hasSideEffects = 0
|
|
|
|
|
|
let Defs = [CCR] in {
|
|
class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
|
|
: MxPseudo<(outs DST.ROp:$dst), (ins SRC.ROp:$src), PAT>;
|
|
|
|
class MxPseudoMove_RM<MxType DST, MxOperand SRCOpd, list<dag> PAT = []>
|
|
: MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>;
|
|
|
|
|
|
// These Pseudos handle loading immediates to registers.
|
|
// They are expanded post-RA into either move or moveq instructions,
|
|
// depending on size, destination register class, and immediate value.
|
|
// This is done with pseudoinstructions in order to not constrain RA to
|
|
// data registers if moveq matches.
|
|
class MxPseudoMove_DI<MxType TYPE>
|
|
: MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.IOp:$src),
|
|
[(set TYPE.ROp:$dst, imm:$src)]>;
|
|
|
|
// i8 imm -> reg can always be converted to moveq,
|
|
// but we still emit a pseudo for consistency.
|
|
def MOVI8di : MxPseudoMove_DI<MxType8d>;
|
|
def MOVI16ri : MxPseudoMove_DI<MxType16r>;
|
|
def MOVI32ri : MxPseudoMove_DI<MxType32r>;
|
|
} // let Defs = [CCR]
|
|
|
|
/// This group of Pseudos is analogues to the real x86 extending moves, but
|
|
/// since M68k does not have those we need to emulate. These instructions
|
|
/// will be expanded right after RA completed because we need to know precisely
|
|
/// what registers are allocated for the operands and if they overlap we just
|
|
/// extend the value if the registers are completely different we need to move
|
|
/// first.
|
|
foreach EXT = ["S", "Z"] in {
|
|
let hasSideEffects = 0 in {
|
|
|
|
def MOV#EXT#Xd16d8 : MxPseudoMove_RR<MxType16d, MxType8d>;
|
|
def MOV#EXT#Xd32d8 : MxPseudoMove_RR<MxType32d, MxType8d>;
|
|
def MOV#EXT#Xd32d16 : MxPseudoMove_RR<MxType32r, MxType16r>;
|
|
|
|
let mayLoad = 1 in {
|
|
|
|
def MOV#EXT#Xd16j8 : MxPseudoMove_RM<MxType16d, MxType8.JOp>;
|
|
def MOV#EXT#Xd32j8 : MxPseudoMove_RM<MxType32d, MxType8.JOp>;
|
|
def MOV#EXT#Xd32j16 : MxPseudoMove_RM<MxType32d, MxType16.JOp>;
|
|
|
|
def MOV#EXT#Xd16p8 : MxPseudoMove_RM<MxType16d, MxType8.POp>;
|
|
def MOV#EXT#Xd32p8 : MxPseudoMove_RM<MxType32d, MxType8.POp>;
|
|
def MOV#EXT#Xd32p16 : MxPseudoMove_RM<MxType32d, MxType16.POp>;
|
|
|
|
def MOV#EXT#Xd16f8 : MxPseudoMove_RM<MxType16d, MxType8.FOp>;
|
|
def MOV#EXT#Xd32f8 : MxPseudoMove_RM<MxType32d, MxType8.FOp>;
|
|
def MOV#EXT#Xd32f16 : MxPseudoMove_RM<MxType32d, MxType16.FOp>;
|
|
|
|
def MOV#EXT#Xd16q8 : MxPseudoMove_RM<MxType16d, MxType8.QOp>;
|
|
def MOV#EXT#Xd32q8 : MxPseudoMove_RM<MxType32d, MxType8.QOp>;
|
|
def MOV#EXT#Xd32q16 : MxPseudoMove_RM<MxType32d, MxType16.QOp>;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
/// This group of instructions is similar to the group above but DOES NOT do
|
|
/// any value extension, they just load a smaller register into the lower part
|
|
/// of another register if operands' real registers are different or does
|
|
/// nothing if they are the same.
|
|
def MOVXd16d8 : MxPseudoMove_RR<MxType16d, MxType8d>;
|
|
def MOVXd32d8 : MxPseudoMove_RR<MxType32d, MxType8d>;
|
|
def MOVXd32d16 : MxPseudoMove_RR<MxType32r, MxType16r>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Extend/Truncate Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// i16 <- sext i8
|
|
def: Pat<(i16 (sext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVSXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARI:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARID:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_ARII:$src),
|
|
(EXTRACT_SUBREG (MOVSXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxSExtLoadi16i8 MxCP_PCD:$src), (MOVSXd16q8 MxPCD8:$src)>;
|
|
|
|
// i32 <- sext i8
|
|
def: Pat<(i32 (sext i8:$src)), (MOVSXd32d8 MxDRD8:$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARI :$src), (MOVSXd32j8 MxARI8 :$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARID:$src), (MOVSXd32p8 MxARID8:$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_ARII:$src), (MOVSXd32f8 MxARII8:$src)>;
|
|
def: Pat<(MxSExtLoadi32i8 MxCP_PCD:$src), (MOVSXd32q8 MxPCD8:$src)>;
|
|
|
|
// i32 <- sext i16
|
|
def: Pat<(i32 (sext i16:$src)), (MOVSXd32d16 MxDRD16:$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARI :$src), (MOVSXd32j16 MxARI16 :$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARID:$src), (MOVSXd32p16 MxARID16:$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_ARII:$src), (MOVSXd32f16 MxARII16:$src)>;
|
|
def: Pat<(MxSExtLoadi32i16 MxCP_PCD:$src), (MOVSXd32q16 MxPCD16:$src)>;
|
|
|
|
// i16 <- zext i8
|
|
def: Pat<(i16 (zext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVZXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARI:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARID:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_ARII:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxZExtLoadi16i8 MxCP_PCD :$src), (MOVZXd16q8 MxPCD8 :$src)>;
|
|
|
|
// i32 <- zext i8
|
|
def: Pat<(i32 (zext i8:$src)), (MOVZXd32d8 MxDRD8:$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARI :$src), (MOVZXd32j8 MxARI8 :$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARID:$src), (MOVZXd32p8 MxARID8:$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_ARII:$src), (MOVZXd32f8 MxARII8:$src)>;
|
|
def: Pat<(MxZExtLoadi32i8 MxCP_PCD :$src), (MOVZXd32q8 MxPCD8 :$src)>;
|
|
|
|
// i32 <- zext i16
|
|
def: Pat<(i32 (zext i16:$src)), (MOVZXd32d16 MxDRD16:$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARI :$src), (MOVZXd32j16 MxARI16 :$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARID:$src), (MOVZXd32p16 MxARID16:$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_ARII:$src), (MOVZXd32f16 MxARII16:$src)>;
|
|
def: Pat<(MxZExtLoadi32i16 MxCP_PCD :$src), (MOVZXd32q16 MxPCD16 :$src)>;
|
|
|
|
// i16 <- anyext i8
|
|
def: Pat<(i16 (anyext i8:$src)),
|
|
(EXTRACT_SUBREG (MOVZXd32d8 MxDRD8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxExtLoadi16i8 MxCP_ARI:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32j8 MxARI8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxExtLoadi16i8 MxCP_ARID:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32p8 MxARID8:$src), MxSubRegIndex16Lo)>;
|
|
def: Pat<(MxExtLoadi16i8 MxCP_ARII:$src),
|
|
(EXTRACT_SUBREG (MOVZXd32f8 MxARII8:$src), MxSubRegIndex16Lo)>;
|
|
|
|
// i32 <- anyext i8
|
|
def: Pat<(i32 (anyext i8:$src)), (MOVZXd32d8 MxDRD8:$src)>;
|
|
def: Pat<(MxExtLoadi32i8 MxCP_ARI :$src), (MOVZXd32j8 MxARI8 :$src)>;
|
|
def: Pat<(MxExtLoadi32i8 MxCP_ARID:$src), (MOVZXd32p8 MxARID8:$src)>;
|
|
def: Pat<(MxExtLoadi32i8 MxCP_ARII:$src), (MOVZXd32f8 MxARII8:$src)>;
|
|
|
|
// i32 <- anyext i16
|
|
def: Pat<(i32 (anyext i16:$src)), (MOVZXd32d16 MxDRD16:$src)>;
|
|
def: Pat<(MxExtLoadi32i16 MxCP_ARI :$src), (MOVZXd32j16 MxARI16 :$src)>;
|
|
def: Pat<(MxExtLoadi32i16 MxCP_ARID:$src), (MOVZXd32p16 MxARID16:$src)>;
|
|
def: Pat<(MxExtLoadi32i16 MxCP_ARII:$src), (MOVZXd32f16 MxARII16:$src)>;
|
|
|
|
// trunc patterns
|
|
def : Pat<(i16 (trunc i32:$src)),
|
|
(EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex16Lo)>;
|
|
def : Pat<(i8 (trunc i32:$src)),
|
|
(EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex8Lo)>;
|
|
def : Pat<(i8 (trunc i16:$src)),
|
|
(EXTRACT_SUBREG MxXRD16:$src, MxSubRegIndex8Lo)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FMOVE
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Defs = [FPS] in
|
|
class MxFMove<string size, dag outs, dag ins, list<dag> pattern,
|
|
string rounding = "">
|
|
: MxInst<outs, ins,
|
|
"f"#rounding#"move."#size#"\t$src, $dst", pattern> {
|
|
// Only FMOVE uses FPC
|
|
let Uses = !if(!eq(rounding, ""), [FPC], []);
|
|
|
|
// FSMOVE and FDMOVE are only available after M68040
|
|
let Predicates = [!if(!eq(rounding, ""), AtLeastM68881, AtLeastM68040)];
|
|
}
|
|
|
|
// FPDR <- FPDR
|
|
class MxFMove_FF<string rounding, int size,
|
|
MxOpBundle Opnd = !cast<MxOpBundle>("MxOp"#size#"AddrMode_fpr")>
|
|
: MxFMove<"x", (outs Opnd.Op:$dst), (ins Opnd.Op:$src),
|
|
[(null_frag)], rounding> {
|
|
let Inst = (ascend
|
|
(descend 0b1111,
|
|
/*COPROCESSOR ID*/0b001,
|
|
0b000,
|
|
/*MODE + REGISTER*/0b000000
|
|
),
|
|
(descend 0b0, /* R/M */0b0, 0b0,
|
|
/*SOURCE SPECIFIER*/
|
|
(operand "$src", 3),
|
|
/*DESTINATION*/
|
|
(operand "$dst", 3),
|
|
/*OPMODE*/
|
|
!cond(!eq(rounding, "s"): 0b1000000,
|
|
!eq(rounding, "d"): 0b1000100,
|
|
true: 0b0000000)
|
|
)
|
|
);
|
|
}
|
|
|
|
foreach rounding = ["", "s", "d"] in {
|
|
def F # !toupper(rounding) # MOV80fp_fp : MxFMove_FF<rounding, 80>;
|
|
|
|
// We don't have `fmove.s` or `fmove.d` because values will be converted to
|
|
// f80 upon storing into the register, but FMOV32/64fp_fp are still needed
|
|
// to make codegen easier.
|
|
let isCodeGenOnly = true in
|
|
foreach size = [32, 64] in
|
|
def F # !toupper(rounding) # MOV # size # fp_fp : MxFMove_FF<rounding, size>;
|
|
}
|
|
// Direction
|
|
defvar MxFMove_FP_EA = false;
|
|
defvar MxFMove_EA_FP = true;
|
|
|
|
// Encoding scheme for FPSYS <-> R/M
|
|
class MxEncFSysMove<bit dir, MxEncMemOp EAEnc, string fsys_reg> {
|
|
dag Value = (ascend
|
|
(descend 0b1111,
|
|
/*COPROCESSOR ID*/0b001,
|
|
0b000,
|
|
/*MODE + REGISTER*/
|
|
EAEnc.EA
|
|
),
|
|
(descend 0b10, /*dir*/ dir,
|
|
/*REGISTER SELECT*/
|
|
(operand "$"#fsys_reg, 3, (encoder "encodeFPSYSSelect")),
|
|
0b0000000000
|
|
)
|
|
);
|
|
}
|
|
|
|
// FPSYS <-> R
|
|
class MxFMove_FSYS_R<string src_reg,
|
|
MxOpBundle SrcOpnd = !cast<MxOpBundle>("MxOp32AddrMode_"#src_reg),
|
|
MxOpBundle DstOpnd = !cond(!eq(src_reg, "d"): MxOp32AddrMode_fpcs,
|
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!eq(src_reg, "a"): MxOp32AddrMode_fpi),
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MxEncMemOp SrcEnc = !cast<MxEncMemOp>("MxMoveSrcOpEnc_"#src_reg)>
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: MxFMove<"l", (outs DstOpnd.Op:$dst), (ins SrcOpnd.Op:$src),
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[(null_frag)]> {
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let Inst = MxEncFSysMove<MxFMove_FP_EA, SrcEnc, "dst">.Value;
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}
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class MxFMove_R_FSYS<string dst_reg,
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MxOpBundle SrcOpnd = !cond(!eq(dst_reg, "d"): MxOp32AddrMode_fpcs,
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!eq(dst_reg, "a"): MxOp32AddrMode_fpi),
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MxOpBundle DstOpnd = !cast<MxOpBundle>("MxOp32AddrMode_"#dst_reg),
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MxEncMemOp DstEnc = !cast<MxEncMemOp>("MxMoveDstOpEnc_"#dst_reg)>
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: MxFMove<"l", (outs DstOpnd.Op:$dst), (ins SrcOpnd.Op:$src),
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[(null_frag)]> {
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let Inst = MxEncFSysMove<MxFMove_EA_FP, DstEnc, "src">.Value;
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}
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def FMOVE32fpcs_d : MxFMove_FSYS_R<"d">;
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def FMOVE32d_fpcs : MxFMove_R_FSYS<"d">;
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def FMOVE32fpi_a : MxFMove_FSYS_R<"a">;
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def FMOVE32a_fpi : MxFMove_R_FSYS<"a">;
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