b01c006f73
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case. This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
346 lines
9.8 KiB
C++
346 lines
9.8 KiB
C++
//===-- M68kInstrInfo.h - M68k Instruction Information ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the M68k implementation of the TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
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#define LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
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#include "M68k.h"
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#include "M68kRegisterInfo.h"
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#include "MCTargetDesc/M68kBaseInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "M68kGenInstrInfo.inc"
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namespace llvm {
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class M68kSubtarget;
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namespace M68k {
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// These MUST be kept in sync with codes definitions in M68kInstrInfo.td
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enum CondCode {
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COND_T = 0, // True
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COND_F = 1, // False
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COND_HI = 2, // High
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COND_LS = 3, // Less or Same
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COND_CC = 4, // Carry Clear
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COND_CS = 5, // Carry Set
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COND_NE = 6, // Not Equal
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COND_EQ = 7, // Equal
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COND_VC = 8, // Overflow Clear
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COND_VS = 9, // Overflow Set
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COND_PL = 10, // Plus
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COND_MI = 11, // Minus
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COND_GE = 12, // Greater or Equal
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COND_LT = 13, // Less Than
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COND_GT = 14, // Greater Than
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COND_LE = 15, // Less or Equal
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LAST_VALID_COND = COND_LE,
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COND_INVALID
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};
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// FIXME would be nice tablegen to generate these predicates and converters
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// mb tag based
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static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Illegal condition code!");
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case M68k::COND_T:
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return M68k::COND_F;
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case M68k::COND_F:
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return M68k::COND_T;
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case M68k::COND_HI:
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return M68k::COND_LS;
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case M68k::COND_LS:
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return M68k::COND_HI;
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case M68k::COND_CC:
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return M68k::COND_CS;
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case M68k::COND_CS:
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return M68k::COND_CC;
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case M68k::COND_NE:
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return M68k::COND_EQ;
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case M68k::COND_EQ:
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return M68k::COND_NE;
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case M68k::COND_VC:
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return M68k::COND_VS;
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case M68k::COND_VS:
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return M68k::COND_VC;
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case M68k::COND_PL:
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return M68k::COND_MI;
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case M68k::COND_MI:
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return M68k::COND_PL;
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case M68k::COND_GE:
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return M68k::COND_LT;
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case M68k::COND_LT:
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return M68k::COND_GE;
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case M68k::COND_GT:
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return M68k::COND_LE;
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case M68k::COND_LE:
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return M68k::COND_GT;
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}
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}
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static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Illegal condition code!");
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case M68k::COND_EQ:
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return M68k::Beq8;
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case M68k::COND_NE:
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return M68k::Bne8;
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case M68k::COND_LT:
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return M68k::Blt8;
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case M68k::COND_LE:
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return M68k::Ble8;
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case M68k::COND_GT:
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return M68k::Bgt8;
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case M68k::COND_GE:
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return M68k::Bge8;
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case M68k::COND_CS:
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return M68k::Bcs8;
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case M68k::COND_LS:
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return M68k::Bls8;
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case M68k::COND_HI:
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return M68k::Bhi8;
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case M68k::COND_CC:
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return M68k::Bcc8;
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case M68k::COND_MI:
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return M68k::Bmi8;
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case M68k::COND_PL:
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return M68k::Bpl8;
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case M68k::COND_VS:
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return M68k::Bvs8;
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case M68k::COND_VC:
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return M68k::Bvc8;
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}
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}
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static inline M68k::CondCode GetCondFromBranchOpc(unsigned Opcode) {
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switch (Opcode) {
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default:
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return M68k::COND_INVALID;
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case M68k::Beq8:
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return M68k::COND_EQ;
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case M68k::Bne8:
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return M68k::COND_NE;
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case M68k::Blt8:
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return M68k::COND_LT;
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case M68k::Ble8:
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return M68k::COND_LE;
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case M68k::Bgt8:
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return M68k::COND_GT;
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case M68k::Bge8:
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return M68k::COND_GE;
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case M68k::Bcs8:
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return M68k::COND_CS;
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case M68k::Bls8:
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return M68k::COND_LS;
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case M68k::Bhi8:
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return M68k::COND_HI;
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case M68k::Bcc8:
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return M68k::COND_CC;
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case M68k::Bmi8:
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return M68k::COND_MI;
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case M68k::Bpl8:
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return M68k::COND_PL;
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case M68k::Bvs8:
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return M68k::COND_VS;
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case M68k::Bvc8:
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return M68k::COND_VC;
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}
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}
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static inline unsigned IsCMP(unsigned Op) {
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switch (Op) {
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default:
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return false;
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case M68k::CMP8dd:
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case M68k::CMP8df:
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case M68k::CMP8di:
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case M68k::CMP8dj:
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case M68k::CMP8dp:
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case M68k::CMP16dr:
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case M68k::CMP16df:
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case M68k::CMP16di:
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case M68k::CMP16dj:
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case M68k::CMP16dp:
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return true;
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}
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}
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static inline bool IsSETCC(unsigned SETCC) {
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switch (SETCC) {
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default:
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return false;
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case M68k::SETd8eq:
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case M68k::SETd8ne:
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case M68k::SETd8lt:
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case M68k::SETd8ge:
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case M68k::SETd8le:
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case M68k::SETd8gt:
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case M68k::SETd8cs:
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case M68k::SETd8cc:
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case M68k::SETd8ls:
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case M68k::SETd8hi:
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case M68k::SETd8pl:
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case M68k::SETd8mi:
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case M68k::SETd8vc:
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case M68k::SETd8vs:
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case M68k::SETj8eq:
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case M68k::SETj8ne:
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case M68k::SETj8lt:
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case M68k::SETj8ge:
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case M68k::SETj8le:
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case M68k::SETj8gt:
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case M68k::SETj8cs:
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case M68k::SETj8cc:
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case M68k::SETj8ls:
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case M68k::SETj8hi:
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case M68k::SETj8pl:
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case M68k::SETj8mi:
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case M68k::SETj8vc:
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case M68k::SETj8vs:
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case M68k::SETp8eq:
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case M68k::SETp8ne:
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case M68k::SETp8lt:
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case M68k::SETp8ge:
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case M68k::SETp8le:
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case M68k::SETp8gt:
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case M68k::SETp8cs:
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case M68k::SETp8cc:
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case M68k::SETp8ls:
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case M68k::SETp8hi:
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case M68k::SETp8pl:
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case M68k::SETp8mi:
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case M68k::SETp8vc:
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case M68k::SETp8vs:
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return true;
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}
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}
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} // namespace M68k
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class M68kInstrInfo : public M68kGenInstrInfo {
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virtual void anchor();
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protected:
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const M68kSubtarget &Subtarget;
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const M68kRegisterInfo RI;
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public:
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explicit M68kInstrInfo(const M68kSubtarget &STI);
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static const M68kInstrInfo *create(M68kSubtarget &STI);
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/// TargetInstrInfo is a superset of MRegister info. As such, whenever a
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/// client has an instance of instruction info, it should always be able to
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/// get register info as well (through this method).
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const M68kRegisterInfo &getRegisterInfo() const { return RI; };
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc, bool RenamableDest = false,
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bool RenamableSrc = false) const override;
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bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
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unsigned &Size, unsigned &Offset,
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const MachineFunction &MF) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register SrcReg,
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bool IsKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override;
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/// Add appropriate SExt nodes
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void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
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/// Add appropriate ZExt nodes
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void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
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/// Move immediate to register
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bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const;
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/// Move across register classes without extension
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bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const;
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/// Move from register and extend
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bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst,
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MVT MVTSrc) const;
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/// Move from memory and extend
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bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned,
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const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
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/// Push/Pop to/from stack
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bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
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bool IsPush) const;
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/// Moves to/from CCR
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bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const;
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/// Expand all MOVEM pseudos into real MOVEMs
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bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
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bool IsRM) const;
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/// Return a virtual register initialized with the global base register
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/// value. Output instructions required to initialize the register in the
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/// function entry block, if necessary.
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
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