fcacda899f
This is no longer tested after other recent changes. AArch64 does have this in their PostLegalizerCombiner.
30 lines
1.0 KiB
TableGen
30 lines
1.0 KiB
TableGen
//=- RISCVCombine.td - Define RISC-V Combine Rules -----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def RISCVPreLegalizerCombiner: GICombiner<
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"RISCVPreLegalizerCombinerImpl", [all_combines]> {
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}
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def RISCVO0PreLegalizerCombiner: GICombiner<
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"RISCVO0PreLegalizerCombinerImpl", [optnone_combines]> {
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}
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// Post-legalization combines which are primarily optimizations.
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// TODO: Add more combines.
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def RISCVPostLegalizerCombiner
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: GICombiner<"RISCVPostLegalizerCombinerImpl",
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[sub_to_add, combines_for_extload, redundant_and,
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identity_combines, shift_immed_chain,
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commute_constant_to_rhs]> {
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}
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