8c17ed1512
selectFPImm previously handled cases where an FPImm could be materialized in an integer register. We can generalize this to cases where a value was in an integer register and then copied to a scalar FP register to be used by a vector instruction. In the affected test, the call lowering code used up all of the FP argument registers and started using GPRs. Now we use integer vector instructions to consume those GPRs instead of moving them to scalar FP first.
285 lines
9.1 KiB
C++
285 lines
9.1 KiB
C++
//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the RISC-V target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/KnownBits.h"
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// RISC-V specific code to select RISC-V machine instructions for
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// SelectionDAG operations.
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namespace llvm {
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class RISCVDAGToDAGISel : public SelectionDAGISel {
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const RISCVSubtarget *Subtarget = nullptr;
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public:
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RISCVDAGToDAGISel() = delete;
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explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
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CodeGenOptLevel OptLevel)
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: SelectionDAGISel(TargetMachine, OptLevel) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<RISCVSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void PreprocessISelDAG() override;
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void PostprocessISelDAG() override;
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void Select(SDNode *Node) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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InlineAsm::ConstraintCode ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset,
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bool IsRV32Zdinx = false);
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bool SelectAddrRegImmRV32Zdinx(SDValue Addr, SDValue &Base, SDValue &Offset) {
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return SelectAddrRegImm(Addr, Base, Offset, true);
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}
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bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
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SDValue &Base, SDValue &Index, SDValue &Scale);
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template <unsigned MaxShift>
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bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Scale) {
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return SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale);
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}
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template <unsigned MaxShift, unsigned Bits>
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bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Scale) {
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if (SelectAddrRegRegScale(Addr, MaxShift, Base, Index, Scale)) {
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if (Index.getOpcode() == ISD::AND) {
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auto *C = dyn_cast<ConstantSDNode>(Index.getOperand(1));
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if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {
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Index = Index.getOperand(0);
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return true;
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}
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}
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}
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return false;
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}
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bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool tryShrinkShlLogicImm(SDNode *Node);
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bool trySignedBitfieldExtract(SDNode *Node);
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bool tryIndexedLoad(SDNode *Node);
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bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
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bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
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return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
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}
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bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
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return selectShiftMask(N, 32, ShAmt);
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}
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bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
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bool selectSETNE(SDValue N, SDValue &Val) {
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return selectSETCC(N, ISD::SETNE, Val);
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}
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bool selectSETEQ(SDValue N, SDValue &Val) {
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return selectSETCC(N, ISD::SETEQ, Val);
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}
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bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
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template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
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return selectSExtBits(N, Bits, Val);
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}
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bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
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template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
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return selectZExtBits(N, Bits, Val);
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}
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bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
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template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
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return selectSHXADDOp(N, ShAmt, Val);
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}
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bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
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template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
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return selectSHXADD_UWOp(N, ShAmt, Val);
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}
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bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
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const unsigned Depth = 0) const;
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bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }
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bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
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bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
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bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
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bool selectVLOp(SDValue N, SDValue &VL);
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bool selectVSplat(SDValue N, SDValue &SplatVal);
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bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
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bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
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template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
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return selectVSplatUimm(N, Bits, Val);
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}
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bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
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bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
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// Matches the splat of a value which can be extended or truncated, such that
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// only the bottom 8 bits are preserved.
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bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
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bool selectScalarFPAsInt(SDValue N, SDValue &Imm);
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bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
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template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
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return selectRVVSimm5(N, Width, Imm);
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}
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void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
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const SDLoc &DL, unsigned CurOp,
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bool IsMasked, bool IsStridedOrIndexed,
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SmallVectorImpl<SDValue> &Operands,
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bool IsLoad = false, MVT *IndexVT = nullptr);
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void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
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void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked);
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void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
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void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
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void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
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void selectVSETVLI(SDNode *Node);
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void selectSF_VC_X_SE(SDNode *Node);
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// Return the RISC-V condition code that matches the given DAG integer
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// condition code. The CondCode must be one of those supported by the RISC-V
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// ISA (see translateSetCCForBranch).
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static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unsupported CondCode");
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case ISD::SETEQ:
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return RISCVCC::COND_EQ;
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case ISD::SETNE:
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return RISCVCC::COND_NE;
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case ISD::SETLT:
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return RISCVCC::COND_LT;
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case ISD::SETGE:
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return RISCVCC::COND_GE;
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case ISD::SETULT:
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return RISCVCC::COND_LTU;
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case ISD::SETUGE:
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return RISCVCC::COND_GEU;
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}
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}
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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private:
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bool doPeepholeSExtW(SDNode *Node);
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bool doPeepholeMaskedRVV(MachineSDNode *Node);
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bool doPeepholeMergeVVMFold();
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bool doPeepholeNoRegPassThru();
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bool performCombineVMergeAndVOps(SDNode *N);
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};
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class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
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public:
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static char ID;
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explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine,
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CodeGenOptLevel OptLevel);
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};
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namespace RISCV {
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struct VLSEGPseudo {
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uint16_t NF : 4;
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uint16_t Masked : 1;
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uint16_t Strided : 1;
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uint16_t FF : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t Pseudo;
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};
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struct VLXSEGPseudo {
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uint16_t NF : 4;
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uint16_t Masked : 1;
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uint16_t Ordered : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t IndexLMUL : 3;
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uint16_t Pseudo;
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};
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struct VSSEGPseudo {
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uint16_t NF : 4;
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uint16_t Masked : 1;
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uint16_t Strided : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t Pseudo;
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};
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struct VSXSEGPseudo {
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uint16_t NF : 4;
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uint16_t Masked : 1;
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uint16_t Ordered : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t IndexLMUL : 3;
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uint16_t Pseudo;
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};
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struct VLEPseudo {
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uint16_t Masked : 1;
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uint16_t Strided : 1;
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uint16_t FF : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t Pseudo;
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};
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struct VSEPseudo {
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uint16_t Masked :1;
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uint16_t Strided : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t Pseudo;
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};
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struct VLX_VSXPseudo {
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uint16_t Masked : 1;
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uint16_t Ordered : 1;
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uint16_t Log2SEW : 3;
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uint16_t LMUL : 3;
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uint16_t IndexLMUL : 3;
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uint16_t Pseudo;
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};
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#define GET_RISCVVSSEGTable_DECL
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#define GET_RISCVVLSEGTable_DECL
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#define GET_RISCVVLXSEGTable_DECL
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#define GET_RISCVVSXSEGTable_DECL
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#define GET_RISCVVLETable_DECL
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#define GET_RISCVVSETable_DECL
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#define GET_RISCVVLXTable_DECL
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#define GET_RISCVVSXTable_DECL
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} // namespace RISCV
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} // namespace llvm
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#endif
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