f6d431f208
Fixes #82659 There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411. Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact. After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.
471 lines
14 KiB
C++
471 lines
14 KiB
C++
//===-- RISCVInsertWriteVXRM.cpp - Insert Write of RISC-V VXRM CSR --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass inserts writes to the VXRM CSR as needed by vector instructions.
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// Each instruction that uses VXRM carries an operand that contains its required
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// VXRM value. This pass tries to optimize placement to avoid redundant writes
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// to VXRM.
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//
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// This is done using 2 dataflow algorithms. The first is a forward data flow
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// to calculate where a VXRM value is available. The second is a backwards
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// dataflow to determine where a VXRM value is anticipated.
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//
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// Finally, we use the results of these two dataflows to insert VXRM writes
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// where a value is anticipated, but not available.
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//
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// FIXME: This pass does not split critical edges, so there can still be some
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// redundancy.
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//
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// FIXME: If we are willing to have writes that aren't always needed, we could
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// reduce the number of VXRM writes in some cases.
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include <queue>
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using namespace llvm;
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#define DEBUG_TYPE "riscv-insert-write-vxrm"
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#define RISCV_INSERT_WRITE_VXRM_NAME "RISC-V Insert Write VXRM Pass"
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namespace {
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class VXRMInfo {
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uint8_t VXRMImm = 0;
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enum : uint8_t {
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Uninitialized,
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Static,
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Unknown,
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} State = Uninitialized;
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public:
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VXRMInfo() {}
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static VXRMInfo getUnknown() {
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VXRMInfo Info;
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Info.setUnknown();
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return Info;
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}
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bool isValid() const { return State != Uninitialized; }
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void setUnknown() { State = Unknown; }
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bool isUnknown() const { return State == Unknown; }
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bool isStatic() const { return State == Static; }
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void setVXRMImm(unsigned Imm) {
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assert(Imm <= 3 && "Unexpected VXRM value");
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VXRMImm = Imm;
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State = Static;
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}
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unsigned getVXRMImm() const {
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assert(isStatic() && VXRMImm <= 3 && "Unexpected state");
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return VXRMImm;
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}
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bool operator==(const VXRMInfo &Other) const {
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// Uninitialized is only equal to another Uninitialized.
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if (State != Other.State)
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return false;
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if (isStatic())
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return VXRMImm == Other.VXRMImm;
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assert((isValid() || isUnknown()) && "Unexpected state");
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return true;
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}
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bool operator!=(const VXRMInfo &Other) const { return !(*this == Other); }
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// Calculate the VXRMInfo visible to a block assuming this and Other are
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// both predecessors.
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VXRMInfo intersect(const VXRMInfo &Other) const {
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// If the new value isn't valid, ignore it.
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if (!Other.isValid())
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return *this;
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// If this value isn't valid, this must be the first predecessor, use it.
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if (!isValid())
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return Other;
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// If either is unknown, the result is unknown.
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if (isUnknown() || Other.isUnknown())
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return VXRMInfo::getUnknown();
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// If we have an exact match, return this.
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if (*this == Other)
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return *this;
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// Otherwise the result is unknown.
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return VXRMInfo::getUnknown();
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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/// Support for debugging, callable in GDB: V->dump()
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LLVM_DUMP_METHOD void dump() const {
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print(dbgs());
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dbgs() << "\n";
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}
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void print(raw_ostream &OS) const {
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OS << '{';
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if (!isValid())
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OS << "Uninitialized";
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else if (isUnknown())
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OS << "Unknown";
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else
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OS << getVXRMImm();
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OS << '}';
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}
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#endif
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};
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_ATTRIBUTE_USED
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inline raw_ostream &operator<<(raw_ostream &OS, const VXRMInfo &V) {
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V.print(OS);
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return OS;
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}
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#endif
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struct BlockData {
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// Indicates if the block uses VXRM. Uninitialized means no use.
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VXRMInfo VXRMUse;
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// Indicates the VXRM output from the block. Unitialized means transparent.
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VXRMInfo VXRMOut;
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// Keeps track of the available VXRM value at the start of the basic bloc.
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VXRMInfo AvailableIn;
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// Keeps track of the available VXRM value at the end of the basic block.
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VXRMInfo AvailableOut;
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// Keeps track of what VXRM is anticipated at the start of the basic block.
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VXRMInfo AnticipatedIn;
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// Keeps track of what VXRM is anticipated at the end of the basic block.
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VXRMInfo AnticipatedOut;
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// Keeps track of whether the block is already in the queue.
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bool InQueue;
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BlockData() = default;
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};
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class RISCVInsertWriteVXRM : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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std::vector<BlockData> BlockInfo;
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std::queue<const MachineBasicBlock *> WorkList;
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public:
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static char ID;
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RISCVInsertWriteVXRM() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return RISCV_INSERT_WRITE_VXRM_NAME;
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}
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private:
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bool computeVXRMChanges(const MachineBasicBlock &MBB);
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void computeAvailable(const MachineBasicBlock &MBB);
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void computeAnticipated(const MachineBasicBlock &MBB);
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void emitWriteVXRM(MachineBasicBlock &MBB);
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};
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} // end anonymous namespace
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char RISCVInsertWriteVXRM::ID = 0;
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INITIALIZE_PASS(RISCVInsertWriteVXRM, DEBUG_TYPE, RISCV_INSERT_WRITE_VXRM_NAME,
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false, false)
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static bool ignoresVXRM(const MachineInstr &MI) {
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switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
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default:
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return false;
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case RISCV::VNCLIP_WI:
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case RISCV::VNCLIPU_WI:
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return MI.getOperand(3).getImm() == 0;
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}
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}
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bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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bool NeedVXRMWrite = false;
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for (const MachineInstr &MI : MBB) {
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int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
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if (VXRMIdx >= 0 && !ignoresVXRM(MI)) {
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unsigned NewVXRMImm = MI.getOperand(VXRMIdx).getImm();
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if (!BBInfo.VXRMUse.isValid())
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BBInfo.VXRMUse.setVXRMImm(NewVXRMImm);
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BBInfo.VXRMOut.setVXRMImm(NewVXRMImm);
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NeedVXRMWrite = true;
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continue;
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}
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if (MI.isCall() || MI.isInlineAsm() ||
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MI.modifiesRegister(RISCV::VXRM, /*TRI=*/nullptr)) {
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if (!BBInfo.VXRMUse.isValid())
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BBInfo.VXRMUse.setUnknown();
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BBInfo.VXRMOut.setUnknown();
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}
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}
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return NeedVXRMWrite;
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}
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void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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BBInfo.InQueue = false;
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VXRMInfo Available;
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if (MBB.pred_empty()) {
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Available.setUnknown();
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} else {
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for (const MachineBasicBlock *P : MBB.predecessors())
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Available = Available.intersect(BlockInfo[P->getNumber()].AvailableOut);
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}
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// If we don't have any valid available info, wait until we do.
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if (!Available.isValid())
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return;
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if (Available != BBInfo.AvailableIn) {
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BBInfo.AvailableIn = Available;
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LLVM_DEBUG(dbgs() << "AvailableIn state of " << printMBBReference(MBB)
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<< " changed to " << BBInfo.AvailableIn << "\n");
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}
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if (BBInfo.VXRMOut.isValid())
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Available = BBInfo.VXRMOut;
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if (Available == BBInfo.AvailableOut)
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return;
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BBInfo.AvailableOut = Available;
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LLVM_DEBUG(dbgs() << "AvailableOut state of " << printMBBReference(MBB)
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<< " changed to " << BBInfo.AvailableOut << "\n");
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// Add the successors to the work list so that we can propagate.
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for (MachineBasicBlock *S : MBB.successors()) {
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if (!BlockInfo[S->getNumber()].InQueue) {
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BlockInfo[S->getNumber()].InQueue = true;
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WorkList.push(S);
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}
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}
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}
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void RISCVInsertWriteVXRM::computeAnticipated(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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BBInfo.InQueue = false;
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VXRMInfo Anticipated;
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if (MBB.succ_empty()) {
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Anticipated.setUnknown();
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} else {
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for (const MachineBasicBlock *S : MBB.successors())
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Anticipated =
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Anticipated.intersect(BlockInfo[S->getNumber()].AnticipatedIn);
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}
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// If we don't have any valid anticipated info, wait until we do.
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if (!Anticipated.isValid())
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return;
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if (Anticipated != BBInfo.AnticipatedOut) {
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BBInfo.AnticipatedOut = Anticipated;
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LLVM_DEBUG(dbgs() << "AnticipatedOut state of " << printMBBReference(MBB)
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<< " changed to " << BBInfo.AnticipatedOut << "\n");
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}
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// If this block reads VXRM, copy it.
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if (BBInfo.VXRMUse.isValid())
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Anticipated = BBInfo.VXRMUse;
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if (Anticipated == BBInfo.AnticipatedIn)
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return;
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BBInfo.AnticipatedIn = Anticipated;
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LLVM_DEBUG(dbgs() << "AnticipatedIn state of " << printMBBReference(MBB)
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<< " changed to " << BBInfo.AnticipatedIn << "\n");
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// Add the predecessors to the work list so that we can propagate.
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for (MachineBasicBlock *P : MBB.predecessors()) {
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if (!BlockInfo[P->getNumber()].InQueue) {
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BlockInfo[P->getNumber()].InQueue = true;
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WorkList.push(P);
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}
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}
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}
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void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {
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const BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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VXRMInfo Info = BBInfo.AvailableIn;
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// Flag to indicates we need to insert a VXRM write. We want to delay it as
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// late as possible in this block.
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bool PendingInsert = false;
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// Insert VXRM write if anticipated and not available.
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if (BBInfo.AnticipatedIn.isStatic()) {
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// If this is the entry block and the value is anticipated, insert.
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if (MBB.isEntryBlock()) {
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PendingInsert = true;
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} else {
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// Search for any predecessors that wouldn't satisfy our requirement and
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// insert a write VXRM if needed.
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// NOTE: If one predecessor is able to provide the requirement, but
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// another isn't, it means we have a critical edge. The better placement
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// would be to split the critical edge.
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for (MachineBasicBlock *P : MBB.predecessors()) {
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const BlockData &PInfo = BlockInfo[P->getNumber()];
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// If it's available out of the predecessor, then we're ok.
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if (PInfo.AvailableOut.isStatic() &&
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PInfo.AvailableOut.getVXRMImm() ==
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BBInfo.AnticipatedIn.getVXRMImm())
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continue;
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// If the predecessor anticipates this value for all its succesors,
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// then a write to VXRM would have already occured before this block is
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// executed.
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if (PInfo.AnticipatedOut.isStatic() &&
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PInfo.AnticipatedOut.getVXRMImm() ==
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BBInfo.AnticipatedIn.getVXRMImm())
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continue;
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PendingInsert = true;
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break;
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}
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}
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Info = BBInfo.AnticipatedIn;
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}
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for (MachineInstr &MI : MBB) {
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int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
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if (VXRMIdx >= 0 && !ignoresVXRM(MI)) {
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unsigned NewVXRMImm = MI.getOperand(VXRMIdx).getImm();
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if (PendingInsert || !Info.isStatic() ||
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Info.getVXRMImm() != NewVXRMImm) {
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assert((!PendingInsert ||
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(Info.isStatic() && Info.getVXRMImm() == NewVXRMImm)) &&
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"Pending VXRM insertion mismatch");
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LLVM_DEBUG(dbgs() << "Inserting before "; MI.print(dbgs()));
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
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.addImm(NewVXRMImm);
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PendingInsert = false;
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}
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MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
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/*IsImp*/ true));
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Info.setVXRMImm(NewVXRMImm);
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continue;
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}
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if (MI.isCall() || MI.isInlineAsm() ||
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MI.modifiesRegister(RISCV::VXRM, /*TRI=*/nullptr))
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Info.setUnknown();
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}
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// If all our successors anticipate a value, do the insert.
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// NOTE: It's possible that not all predecessors of our successor provide the
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// correct value. This can occur on critical edges. If we don't split the
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// critical edge we'll also have a write vxrm in the succesor that is
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// redundant with this one.
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if (PendingInsert ||
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(BBInfo.AnticipatedOut.isStatic() &&
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(!Info.isStatic() ||
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Info.getVXRMImm() != BBInfo.AnticipatedOut.getVXRMImm()))) {
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assert((!PendingInsert ||
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(Info.isStatic() && BBInfo.AnticipatedOut.isStatic() &&
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Info.getVXRMImm() == BBInfo.AnticipatedOut.getVXRMImm())) &&
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"Pending VXRM insertion mismatch");
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LLVM_DEBUG(dbgs() << "Inserting at end of " << printMBBReference(MBB)
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<< " changing to " << BBInfo.AnticipatedOut << "\n");
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BuildMI(MBB, MBB.getFirstTerminator(), DebugLoc(),
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TII->get(RISCV::WriteVXRMImm))
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.addImm(BBInfo.AnticipatedOut.getVXRMImm());
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}
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}
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bool RISCVInsertWriteVXRM::runOnMachineFunction(MachineFunction &MF) {
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// Skip if the vector extension is not enabled.
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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if (!ST.hasVInstructions())
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return false;
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TII = ST.getInstrInfo();
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assert(BlockInfo.empty() && "Expect empty block infos");
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BlockInfo.resize(MF.getNumBlockIDs());
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// Phase 1 - collect block information.
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bool NeedVXRMChange = false;
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for (const MachineBasicBlock &MBB : MF)
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NeedVXRMChange |= computeVXRMChanges(MBB);
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if (!NeedVXRMChange) {
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BlockInfo.clear();
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return false;
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}
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// Phase 2 - Compute available VXRM using a forward walk.
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for (const MachineBasicBlock &MBB : MF) {
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WorkList.push(&MBB);
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BlockInfo[MBB.getNumber()].InQueue = true;
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}
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while (!WorkList.empty()) {
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const MachineBasicBlock &MBB = *WorkList.front();
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WorkList.pop();
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computeAvailable(MBB);
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}
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// Phase 3 - Compute anticipated VXRM using a backwards walk.
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for (const MachineBasicBlock &MBB : llvm::reverse(MF)) {
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WorkList.push(&MBB);
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BlockInfo[MBB.getNumber()].InQueue = true;
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}
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while (!WorkList.empty()) {
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const MachineBasicBlock &MBB = *WorkList.front();
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WorkList.pop();
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computeAnticipated(MBB);
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}
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// Phase 4 - Emit VXRM writes at the earliest place possible.
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for (MachineBasicBlock &MBB : MF)
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emitWriteVXRM(MBB);
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BlockInfo.clear();
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return true;
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}
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FunctionPass *llvm::createRISCVInsertWriteVXRMPass() {
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return new RISCVInsertWriteVXRM();
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}
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