e1495283cf
RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.
We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024
So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.
163 lines
7.8 KiB
TableGen
163 lines
7.8 KiB
TableGen
//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Profile Featuyre Lists
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//===----------------------------------------------------------------------===//
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// RVI Profile Family
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defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
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defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI];
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// RVA Profile Family
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defvar RVA20U64BaseFeatures = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm];
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defvar RVA20U64Features = !listconcat(RVA20U64BaseFeatures,
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[FeatureStdExtZa128rs]);
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defvar RVA20S64BaseFeatures = [FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala];
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defvar RVA20S64Features = !listconcat(RVA20U64Features,
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RVA20S64BaseFeatures);
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defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures,
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[FeatureStdExtZa64rs,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtB,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt]);
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defvar RVA22S64BaseFeatures = !listconcat(RVA20S64BaseFeatures,
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[FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval]);
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defvar RVA22S64Features = !listconcat(RVA22U64Features,
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RVA22S64BaseFeatures);
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defvar RVA23U64Features = !listconcat(RVA22U64Features,
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[FeatureStdExtV,
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FeatureStdExtZvfhmin,
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FeatureStdExtZvbb,
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FeatureStdExtZvkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs,
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FeatureStdExtSupm]);
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defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures,
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[FeatureStdExtSvnapot,
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FeatureStdExtSstc,
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FeatureStdExtSscofpmf,
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FeatureStdExtSsnpm,
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FeatureStdExtSsu64xl,
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FeatureStdExtSha]);
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defvar RVA23S64Features = !listconcat(RVA23U64Features,
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RVA23S64BaseFeatures);
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// RVB Profile Family
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defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures,
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[FeatureStdExtZihpm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihintpause,
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FeatureStdExtB,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs]);
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defvar RVB23S64Features = !listconcat(RVB23U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvnapot,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
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FeatureStdExtSstc,
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FeatureStdExtSscofpmf,
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FeatureStdExtSsu64xl]);
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// RVM Profile Family
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defvar RVM23U32Features = [Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtB,
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FeatureStdExtZicond,
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FeatureStdExtZihintpause,
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FeatureStdExtZihintntl,
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FeatureStdExtZce,
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FeatureStdExtZicbop,
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FeatureStdExtZimop,
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FeatureStdExtZcmop];
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//===----------------------------------------------------------------------===//
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// Profile Definitions for ISA String
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//===----------------------------------------------------------------------===//
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class RISCVProfile<string name, list<SubtargetFeature> features>
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: SubtargetFeature<name, "Is" # NAME, "true",
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"RISC-V " # name # " profile", features> {
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// Indicates if the profile is not yet ratified, so should be treated as
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// experimental.
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bit Experimental = false;
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}
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class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
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: RISCVProfile<"experimental-"#name, features> {
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let Experimental = true;
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}
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def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>;
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def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>;
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def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;
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def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>;
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def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>;
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def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>;
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def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>;
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def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>;
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def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>;
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def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>;
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def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>;
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