ca63860733
This change makes sure the preferred switch condition int type size remains the same throughout CodeGen optimizations. The change fixes running several OpenCL applications with -O2 or higher opt levels, and fixes Basic/stream/stream_max_stmt_exceed.cpp DPC++ E2E test with -O2.
80 lines
3.0 KiB
C++
80 lines
3.0 KiB
C++
//===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SPIR-V uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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#include "SPIRVGlobalRegistry.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include <set>
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namespace llvm {
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class SPIRVSubtarget;
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class SPIRVTargetLowering : public TargetLowering {
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const SPIRVSubtarget &STI;
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// Record of already processed machine functions
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mutable std::set<const MachineFunction *> ProcessedMF;
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public:
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explicit SPIRVTargetLowering(const TargetMachine &TM,
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const SPIRVSubtarget &ST)
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: TargetLowering(TM), STI(ST) {}
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// Stop IRTranslator breaking up FMA instrs to preserve types information.
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT) const override {
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return true;
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}
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// prevent creation of jump tables
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bool areJTsAllowed(const Function *) const override { return false; }
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// This is to prevent sexts of non-i64 vector indices which are generated
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// within general IRTranslator hence type generation for it is omitted.
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MVT getVectorIdxTy(const DataLayout &DL) const override {
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return MVT::getIntegerVT(32);
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}
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
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EVT VT) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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unsigned
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getNumRegisters(LLVMContext &Context, EVT VT,
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std::optional<MVT> RegisterVT = std::nullopt) const override {
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return 1;
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}
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// Call the default implementation and finalize target lowering by inserting
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// extra instructions required to preserve validity of SPIR-V code imposed by
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// the standard.
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void finalizeLowering(MachineFunction &MF) const override;
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MVT getPreferredSwitchConditionType(LLVMContext &Context,
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EVT ConditionVT) const override {
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return ConditionVT.getSimpleVT();
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}
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
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